NDLI: Incremental reconfiguration of multi-FPGA systems

Please wait, while we are loading the content...

Interconnect enhancements for a high-speed PLD architecture

A faster distributed arithmetic architecture for FPGAs

Efficient circuit clustering for area and power reduction in FPGAs

Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method

Constrained clock shifting for field programmable gate arrays

On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques

Performance-constrained pipelining of software loops onto reconfigurable hardware

Parallel-beam backprojection: an FPGA implementation optimized for medical imaging

FPGA switch block layout and evaluation

Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

Integrated retiming and placement for field programmable gate arrays

FPGA implementation of neighborhood-of-four cellular automata random number generators

Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series

Dynamic power consumption in Virtex™-II FPGA family

Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation

A dynamically reconfigurable adaptive viterbi decoder

Circuit design of routing switches

A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs

SPFD-based global rewiring

Cryptographic rights management of FPGA intellectual property cores

FPGA test time reduction through a novel interconnect testing scheme

Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip

Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine

Data reorganization engines for the next generation of system-on-a-chip FPGAs

EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits

Incremental reconfiguration of multi-FPGA systems

Content Provider	ACM Digital Library
Author	Lee, K. K. Wong, D. F.
Abstract	In reconfigurable computing, circuits implemented on multi-FPGA systems have to be incrementally modified. Since reconfiguring an FPGA is time-consuming, the time for reconfiguration depends on the number of FPGAs to be reconfigured. Our objective is to reduce the number of such FPGAs. In this paper, we consider the specific problem of incrementally reconfiguring a multi-FPGA system that utilizes the direct interconnection architecture, where routing connections between FPGAs are to neighbors that are near. This problem can be divided into a net addition problem and a net deletion problem. We show that the net addition problem is a generalization of the NP-complete Steiner tree problem. Our algorithm for this problem is based on an adaptation of the Klein-Ravi approximation algorithm for the node-weighted Steiner tree problem. As for the net deletion problem, we prove that it is NP-complete but the problem is solvable in polynomial time for tree topologies. Based on the algorithm for trees, we design an effective heuristic algorithm for the general net deletion problem. Finally, we present an algorithm for solving the incremental reconfiguration problem which handles both placement of new gates and inter-FPGA routing.
Starting Page	206
Ending Page	213
Page Count	8
File Format	PDF
ISBN	1581134525
DOI	10.1145/503048.503078
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-02-24
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Wong: Incremental Reconfiguration of Multi-FPGA Systems (2002)

Efficient dynamic reconfiguration for multi-context embedded FPGA

Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays

Incremental Reconfiguration for Pipelined Applications

A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms

Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems

Fine-Grained Manipulation of FPGA Configuration for Incremental Design

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

Incremental Reconfiguration for Pipelined Applications (1997)

Incremental reconfiguration of multi-FPGA systems

Similar Documents

Wong: Incremental Reconfiguration of Multi-FPGA Systems (2002)

Efficient dynamic reconfiguration for multi-context embedded FPGA

Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays

Incremental Reconfiguration for Pipelined Applications

A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms

Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems

Fine-Grained Manipulation of FPGA Configuration for Incremental Design

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

Incremental Reconfiguration for Pipelined Applications (1997)

Incremental reconfiguration of multi-FPGA systems