NDLI: Design Trade-Offs in High-Throughput Coherence Controllers

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Single-Chip Multiprocessors: The Rebirth of Parallel Processing

Constraint Graph Analysis of Multithreaded Programs

The Impact of Resource Partitioning on SMT Processors

Initial Observations of the Simultaneous Multithreading Pentium 4 Processor

Efficient Resource Management during Instruction Scheduling for the EPIC Architecture

Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency

Y-Branches: When You Come to a Fork in the Road, Take It

Optimizing Program Locality Through CMEs and GAs

Miss Rate Prediction across All Program Inputs

Compiler-Directed Content-Aware Prefetching for Dynamic Data Structures

Challenges and New Approaches to Program Analysis

Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems

Inter-Procedural Loop Fusion, Array Contraction and Rotation

Spill Code Minimization by Spill Code Motion

Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU

An Efficient Online Path Profiling Framework for Java Just-In-Time Compilers

Compressing Extended Program Traces Using Value Predictors

Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation

Reactive Multi-Word Synchronization for Multiprocessors

Design Trade-Offs in High-Throughput Coherence Controllers

Memory Hierarchy Design for a Multiprocessor Look-up Engine

Biomedical Computing and Visualization

Characterizing and Predicting Program Behavior and its Variability

Redeeming IPC as a Performance Metric for Multithreaded Programs

Picking Statistically Valid and Early Simulation Points

Reducing Datapath Energy through the Isolation of Short-Lived Operands

Resolving Register Bank Conflicts for a Network Processor

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Design Trade-Offs in High-Throughput Coherence Controllers

Content Provider	ACM Digital Library
Author	Nguyen, Anthony-Trung Torrellas, Josep
Abstract	Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose to take microarchitectural enhancements used for microprocessors and apply them to improve the throughput of hardwired CCs. These enhancements are CC support for nonblocking execution, early fetches of directory and L3 information, and superpipelining. Nonblocking execution in the CC reduces stalls by processing subsequent coherence transactions in the presence of misses in the directory cache and tag cache. Early fetching in the CC hides misses in the directory and tag caches and, therefore, also removes stalls. Finally, superpipelining in the CC increases its processing bandwidth. These supports all serve to increase the overall throughput of CCs and improve overall system performance.Using both SPLASH-2 and parallelized SPEC95 applications on detailed simulation models, we show that CCs that support nonblocking execution and superpipelining boost the performance of machines substantially. With these CCs, a 64-processor machine with four nodes of four SMPs per node runs on average 3.56 times faster than if it used conventional CCs. In addition, the machine runs about as fast as a more costly 64-processor machine with sixteen nodes of one SMP per node and the same advanced CCs. This is despite using much less network, chassis, and node hardware. Consequently, with our proposed advanced CCs, we can reduce the system cost signi.cantly without affecting performance.
ISBN	0769520219
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-09-27
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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