NDLI: The Collie: a wait-free compacting collector

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The Collie: a wait-free compacting collector

Content Provider	ACM Digital Library
Author	Gehringer, Edward Wolf, Michael Tene, Gil Iyengar, Balaji
Abstract	We describe the Collie collector, a fully concurrent compacting collector that uses transactional memory techniques to achieve wait-free compaction. The collector uses compaction as the primary means of reclaiming unused memory, and performs "individual object transplantations" as transactions. We introduce new terms and requirements useful for analyzing concurrent relocating collectors, including definitions of referrer sets, object transplantation and the notion of individually transplantable objects. The Collie collector builds on these terms and on a detailed analysis of an object's legal states during compaction. Collie uses a combination of read barriers, write barriers and transactional memory operations. Its read-barrier supports fast, direct object referencing while using a bound, constant time, wait- free triggering path. Collie thereby avoids the constant indirection cost of Brooks [9] style barriers or handle-based heaps [25]. Collie is demonstrated using speculative multi-address atomicity [11], a form of hardware transactional memory supported by the Azul Vega architecture [2]. We evaluate the Collie collector on the Azul platform, on which previous concurrent collectors such as the Pauseless Collector [12] and its generational variant [30] have been commercially available for several years. We discuss Collie's performance while running sustained workloads, and compare it to the Pauseless collector on the same platform. The Collie collector provides significant MMU [5] improvements even in the 1-msec time windows compared to the Pauseless collector. At the same time, it matches Pauseless in throughput and in the ability to scale to large heap sizes. We believe that the Collie collector is the first garbage collector to leverage hardware-assisted transactional memory. While Collie directly leverages Vega's speculative multi-address atomicity feature (SMA) [11], its design can be easily adapted to other hardware- assisted transactional memory systems. Specifically, the upcoming Intel TSX instruction set extensions [21] include capabilities similar to SMA. We expect Collie to be easily implementable on future commodity servers based on Intel Haswell processors and following processor generations.
Starting Page	85
Ending Page	96
Page Count	12
File Format	PDF
ISBN	9781450313506
DOI	10.1145/2258996.2259009
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-06-15
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Garbage collection Minimum mutator utilization Memory management Virtual memory Concurrent Runtime systems Read barrier Atomicity primitives Compaction Transactional memory
Content Type	Text
Resource Type	Article

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