NDLI: Construction of minimal functional skew clock trees

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Construction of minimal functional skew clock trees

Content Provider	ACM Digital Library
Author	Ramachandran, Venky
Abstract	Power is the number one implementation challenge for many consumer SoCs, especially in the telecommunications and mobile space. A large portion of that, 30% or more, can be directly attributed to the clock tree. 10-20% additional power can additionally be attributed to increased logic area on account of skew in the clock tree. Increasingly, we find designers trying to reduce power both by manual specifications of multiple voltage and power domains, block and core level clock gating as well as more automated techniques like leaf-level combinational and sequential clock gating. However, this tends to increase the problem complexity for the clock tree synthesis tool. Furthermore, these numbers are only likely to get worse with larger designs and more complex clocking scenarios. Already it is not uncommon to see over 200 clocks defined for a modern SoC; several of them asynchronous to each other in the timing sense; but which nevertheless overlap physically. This creates a nightmare problem instance for traditional clock tree synthesis tools attempting to balance path delays to all sinks. Further, due to DFT and other design considerations, the clock tree network is increasingly resembling more a regular logic network of gates rather than a simple buffer tree with the occasional clock gates. The premise of this paper, backed by experimental data on real designs, is that the clock tree synthesis problem for complex SoCs needs to be done in a true timing driven fashion where the delay requirements are automatically derived from the timing constraints themselves. One key observation is that global skew constraints is not only unnecessary, but could indeed be harmful to the goals of building reduced power but timing friendly clock trees. Power reduction is achieved through lower buffer counts brought upon by the relaxed balancing requirements. By considering only the true timing paths in the design, the real impact of functional skew in the clock tree can be more appropriately determined and considered during the tree building process itself. As such the CTS solution could borrow from some of the timing driven techniques of the physical synthesis world that have been developed for reducing total negative slack. Moreover, this needs to happen in a tight incremental loop, where the timing impact of refining or rebuilding some portion of the clock tree can be immediately analyzed and acted upon. Care should be exercised in this process not to over-buffer to make some marginal timing improvement. For instance some initial clustering can often be done to group related registers, and the clock to all such registers can be shifted together.
Starting Page	119
Ending Page	120
Page Count	2
File Format	PDF
ISBN	9781450311670
DOI	10.1145/2160916.2160943
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-03-25
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Clock tree synthesis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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