NDLI: Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization

Please wait, while we are loading the content...

An arbiter based on-chip droop detector system

VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip

Efficient shift-adds design of digit-serial multiple constant multiplications

Design techniques to improve the device write margin for MRAM-based cache memory

A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates

Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation

An efficient algorithm for custom instruction enumeration

A 65 nm CMOS low power RF front-end for L1/E1 GPS/Galileo signals

Layout-aware variation evaluation of analog circuits and its validity on op-amp designs

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

Power estimation of dividers implemented in FPGAs

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

Robust signaling techniques for through silicon via bundles

SMECY: smart multi-core embedded systems

Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design

Hardware security in VLSI

Quantum devices and optical computing: introduction

A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctions

Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs

Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAs

DRAM energy reduction by prefetching-based memory traffic clustering

A $45.6μ^{2}$ 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS

Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study

An approximation algorithm for cofactoring-based synthesis

Simulation-based equivalence checking between SystemC models at different levels of abstraction

A linear programming approach for minimum NBTI vector selection

Redundancy in SAR ADCs

Nanometer-scale standard cell library for enhanced redundant via1 insertion rate

Power efficient partial product compression

Efficient realization of RTD-CMOS logic gates

Design of MRAM based logic circuits and its applications

Integrated circuits metering for piracy protection and digital rights management: an overview

Optically leviting dielectrics in the quantum regime

Logic synthesis for integrated optics

Run-time energy management of manycore systems through reconfigurable interconnects

FPGA implementation of binary edwards curve usingternary representation

A low-power TCAM design using mask-aware match-line (MAML) technique

A new balanced 4-moduli set $\{2^{k},$ $2^{n}$ - 1, $2^{n}$ + 1, $2^{n+1}-1\}$ and its reverse converter design for efficient fir filter implementation

Reconfigurable controllers for synchronization via wagging

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization

Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochips

Fitting standard cell performance to generalized Lambda distributions

A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics

Circuit design of a dual-versioning L1 data cache for optimistic concurrency

Evaluation of FPGA routing architectures under process variation

On residue removal in digital microfluidic biochips

Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry

Physically unclonable functions: manufacturing variability as an unclonable device identifier

Quantum information processing beyond polarization encoding

Fine-grain reconfigurable logic cells based on double-gate CNTFETs

Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology

Design of low-power multiple constant multiplications using low-complexity minimum depth operations

Hardware-assisted dynamic power and thermal management in multi-core SoCs

Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective

Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays

New optimal layer assignment for bus-oriented escape routing

A countermeasure against power analysis attacks for FSR-based stream ciphers

Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits

Buffering of frequent accesses for reduced cache aging

Real-time address trace compression for emulated and real system-on-chip processor core debugging

High resolution MASH 2-2 Sigma Delta interface for capacitive accelerometers

Repeater insertion in power-managed VLSI systems

Enabling architectural innovations using non-volatile memory

The future of high-speed cryptography: new computing platforms and new ciphers

Solid state optical quantum memories

RAMA: a self-assembled multiferroic magnetic QCA for low power systems

Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip

High performance technique for database applications using a hybrid GPU/CPU platform

A 7T SRAM bit-cell for low-power embedded memories

A design methodology for the automatic sizing of standard-cell libraries

Acceleration of random-walk-based linear circuit analysis using importance sampling

Low jitter audio range PLL with ultra low power dissipation

Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization

Combined architecture and hardening techniques exploration for reliable embedded system design

Investigating modern layout representations for improved 3d design automation

Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasures

Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM

Challenges for non-volatile memory & logic manufacturing utilizing magnetic tunnel junction on 300 mm wafer

Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers

Design and management of 3D-stacked NUCA cache for chip multiprocessors

Ordered coloring-based resource binding for datapaths with improved skew-adjustability

A new low power and area efficient semi-digital PLL architecture for low bandwidth applications

Handling intra-die variations in PSTA

SIAR: splitting-graph-based interactive analog router

Integrated logic synthesis using simulated annealing

A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs

A geometric programming aided knowledge based approach for analog circuit synthesis and sizing

Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization

Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect

A dual-core system solution for wearable health monitors

Efficient method to compute minimum decision chains of Boolean functions

Time-mode reconstruction iir filters for ΣΔ phase modulation applications

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization

Content Provider	ACM Digital Library
Author	Yao, Hailong Zhou, Qiang Sze, C. N. Niu, Feifei Yang, Jianlei Cai, Yici
Abstract	Buered clock tree synthesis (CTS) is increasingly critical as VLSI technology continually scales down. Many researches have been done on this topic due to its key role in CTS, but current approaches either lack the obstacle-avoiding functionality or lead to large clock latency and/or skew. This paper presents a new obstacle-avoiding CTS approach with separate clock tree construction and buer insertion stages based on an integral view to explore the global optimization space. Aiming at skew optimization under constraints of slew and obstacles, our CTS approach features the clock tree construction stage with the obstacle-aware topology generation algorithm called OBB, balanced insertion of candidate buer positions, and a fast heuristic buer insertion algorithm. Experimental results show the eectiveness of our CTS approach with significantly improved skew and latency than [6] by 46% and 63% on average, and 15.3% reduction in skew than [5]. Our OBB heuristic obtains 36% improvement in skew than the classic balanced bipartition algorithm (BB) in [10].
Starting Page	199
Ending Page	204
Page Count	6
File Format	PDF
ISBN	9781450306676
DOI	10.1145/1973009.1973049
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-05-02
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Obstacle avoidance Buffer insertion Clock tree synthesis Slew Skew optimization
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in