NDLI: Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling

Please wait, while we are loading the content...

Software Transactional Memory for GPU Architectures

Red Fox: An Execution Environment for Relational Query Processing on GPUs

Call Paths for Pin Tools

DeltaPath: Precise and Scalable Calling Context Encoding

Static Reference Analysis for GUI Objects in Android Software

Non-affine Extensions to Polyhedral Code Generation

Security Signature Inference for JavaScript-based Browser Addons

Adaptive Mapping and Parameter Selection Scheme to Improve Automatic Code Generation for GPUs

Warm-Up Simulation Methodology for HW/SW Co-Designed Processors

Just-In-Time Software Pipelining

Portable and Transparent Host-Device Communication Optimization for GPGPU Environments

LeakChecker: Practical Static Memory Leak Detection for Managed Languages

Dynamic and Adaptive Calling Context Encoding

Accelerating Dynamic Detection of Uses of Undefined Values with Static Value-Flow Analysis

Single Assignment Compiler, Single Assignment Architecture: Future Gated Single Assignment Form*; Static Single Assignment with Congruence Classes

Estimating the Empirical Cost Function of Routines with Dynamic Workloads

Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling

Optimizing R VM: Allocation Removal and Path Length Reduction via Interpreter-level Specialization

A Basic Linear Algebra Compiler

Hybrid Hexagonal/Classical Tiling for GPUs

DrDebug: Deterministic Replay based Cyclic Debugging with Dynamic Slicing

Fine-grained Benchmark Subsetting for System Selection

Partial Escape Analysis and Scalar Replacement for Java

Simplifying Scalable Graph Processing with a Domain-Specific Language

Automated Algorithmic Error Resilience for Structured Grid Problems Based on Outlier Detection

Fluidic Kernels: Cooperative Execution of OpenCL Programs on Multiple Heterogeneous Devices

Extending the PCRE Library with Static Backtracking Based Just-in-Time Compilation Support

Efficient Mapping of Irregular C++ Applications to Integrated GPUs

WatchdogLite: Hardware-Accelerated Compiler-Based Pointer Checking

Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling

Content Provider	ACM Digital Library
Author	Black-Schaffer, David Koukos, Konstantinos Jimborean, Alexandra Kaxiras, Stefanos Spiliopoulos, Vasileios
Abstract	Traditional compiler approaches to optimize power efficiency aim to adjust voltage and frequency at runtime to match the code characteristics to the hardware (e.g., running memory-bound phases at a lower frequency). However, such approaches are constrained by three factors: (i) voltage-frequency transitions are too slow to be applied at instruction granularity, (ii) larger code regions are seldom unequivocally memory- or compute-bound, and, (iii) the available voltage scaling range for future technologies is rapidly shrinking. These factors necessitate new approaches to address power-efficiency at the code-generation level. This paper proposes one such approach to automatically generate power-efficient code using a decoupled access/execute (DAE) model. In DAE a program is split into tasks, where each task consists of two sufficiently coarse-grained phases to enable effective Dynamic Voltage Frequency Scaling (DVFS): (i) the access-phase for data prefetch (heavily memory-bound), and (ii) the execute-phase that performs the actual computation (heavily compute-bound). Our contribution is to provide a compiler methodology to automatically generate the access-phases for a task-based programming system. Our approach is capable of handling both affine (through a polyhedral analysis) and non-affine codes (through optimized task skeletons). Our evaluation shows that the automatically generated versions improve EDP by 25% on average compared to a coupled execution, without any performance degradation, and surpasses the EDP savings of the corresponding hand-crafted tasks by 5%.
Starting Page	262
Ending Page	272
Page Count	11
File Format	PDF
ISBN	9781450326704
DOI	10.1145/2544137.2544161
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-02-15
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Decoupled execution Polyhedral model Energy Compiler optimizations Performance Dvfs Task-based execution
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Towards more efficient execution: a decoupled access-execute approach

Learning based DVFS for simultaneous temperature, performance and energy management

Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation (2004)

Energy-aware system design compiler methods for multiprocessors and Voltage Scaling/frequency

A dynamic compilation framework for controlling microprocessor energy and performance

The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU

Pre- and post selection of compiler optimizations by program execution.

Multiprocessor Global Scheduling on Frame-Based DVFS Systems (2009)

Compiler-Directed Dynamic Voltage Scaling Based on Program Regions (2001)

Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling

Similar Documents

Towards more efficient execution: a decoupled access-execute approach

Learning based DVFS for simultaneous temperature, performance and energy management

Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation (2004)

Energy-aware system design compiler methods for multiprocessors and Voltage Scaling/frequency

A dynamic compilation framework for controlling microprocessor energy and performance

The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU

Pre- and post selection of compiler optimizations by program execution.

Multiprocessor Global Scheduling on Frame-Based DVFS Systems (2009)

Compiler-Directed Dynamic Voltage Scaling Based on Program Regions (2001)

Fix the code. Don't tweak the hardware: A new compiler approach to Voltage-Frequency scaling