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  1. Proceedings of International Workshop on Manycore Embedded Systems (MES '14)
  2. Adaptive Compute-phase Prediction and Thread Prioritization to Mitigate Memory Access Latency
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Adaptive Cache Bypass and Insertion for Many-core Accelerators
On the Relevance of Architectural Awareness for Efficient Fork/Join Support on Cluster-Based Manycores
A Low-resource and Scalable Strategy for Segment Partitioning of Many-core Nano Networks
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks
A Virtualization Framework for IOMMU-less Many-Core Accelerators
Acceleration of Software Transactional Memory through Hardware Clock
Adaptive Compute-phase Prediction and Thread Prioritization to Mitigate Memory Access Latency
A GALS Router for Asynchronous Network-on-Chip
Hardware Threading Techniques for Multi-Threaded MPSoCs
A Closed Loop Control based Power Manager for WiNoC Architectures
Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures

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Adaptive Compute-phase Prediction and Thread Prioritization to Mitigate Memory Access Latency

Content Provider ACM Digital Library
Author Akturk, Ismail Ozturk, Ozcan
Abstract The full potential of chip multiprocessors remains unexploited due to the thread oblivious memory access schedulers used in off-chip main memory controllers. This is especially pronounced in embedded systems due to limitations in memory. We propose an adaptive compute-phase prediction and thread prioritization algorithm for memory access scheduling for embedded chip multiprocessors. The proposed algorithm efficiently categorize threads based on execution characteristics and provides fine-grained prioritization that allows to differentiate threads and prioritize their memory access requests accordingly. The threads in compute phase are prioritized among the threads in memory phase. Furthermore, the threads in compute phase are prioritized among themselves based on the potential of making more progress in their execution. Compared to the prior works First-Ready First-Come First-Serve (FR-FCFS) and Compute-phase Prediction with Writeback-Refresh Overlap (CP-WO), the proposed algorithm reduces the execution time of the generated workloads up to 23.6% and 12.9%, respectively.
Starting Page 48
Ending Page 51
Page Count 4
File Format PDF
ISBN 9781450328227
DOI 10.1145/2613908.2613919
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2014-06-15
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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