NDLI: Processor autonomy on SIMD architectures

Please wait, while we are loading the content...

Graph contraction for physical optimization methods: a quality-cost tradeoff for mapping data on parallel computers

Managing pages in shared virtual memory systems: getting the compiler into the game

The EM-4 under implicit parallelism

Toward a methodology of optimizing programs for high-performance computers

Data stream control optimization in dataflow architectures

The effectiveness of decoupling

Speculative prefetching

Increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Speculative execution and branch prediction on parallel machines

PARADIGM: a compiler for automatic data distribution on multicomputers

A massively parallel optimizer for expression evaluation

Static and dynamic evaluation of data dependence analysis

Performance analysis of four SIMD machines

Processor autonomy on SIMD architectures

Exact side effects for interprocedural dependence analysis

CMAX: a Fortran translator for the connection machine system

Scalable parallel memory architecture with a skew scheme

EMC-Y: parallel processing element optimizing communication and computation

Toward automatic partitioning of arrays on distributed memory computers

Dynamic control of performance monitoring on large scale parallel systems

Anatomy of a message in the Alewife multiprocessor

A static parameter based performance prediction tool for parallel programs

Empirical study of latency hiding on a fine-grain parallel processor

The NuMesh: a modular, scalable communications substrate

Evaluating the communication performance of MPPs using synthetic sparse matrix multiplication workloads

Super-threading: architectural and software mechanisms for optimizing parallel computation

Parallel direct solution of large sparse systems in finite element computations

Parallel triangular decompositions of an oil refining simulation

Parallel eigenanalysis for nested grids

Parallel processing architecture for the Hitachi S-3800 shared-memory vector multiprocessor

A scalar architecture for pseudo vector processing based on slide-windowed registers

A micro-vectorprocessor architecture: performance modeling and benchmarking

Performance prediction of parallel processing systems: the PAMELA methodology

Dynamic switching of coherent cache protocols and its effects on Doacross loops

Effects of memory latencies on non-blocking processor/cache architectures

A cellular automation methodology for solving the wave equation

Parallel two-level simulated annealing

An experimental performance evaluation of Touchstone Delta Concurrent File System

A high-performance parallel database architecture

File archive activity in a supercomputing environment

A proposal of Level 3 interface for band and skyline matrix factorization subroutine

Partitioning the statement per iteration space using non-singular matrices

Compilation techniques for sparse matrix computations

Processor autonomy on SIMD architectures

Content Provider	ACM Digital Library
Author	Narayanan, P. J.
Abstract	Flynn classified high speed (parallel) computers into four categories. Of these, the single instruction stream, multiple data stream (SIMD) processor array machines have become very popular in practical parallel processing. The commercially available processor array machines display important architectural variety, while belonging to SIMD category of machines. In this paper, we further categorize the SIMD class of machines on the basis of processor autonomy of the machines, which is the capability of the individual processing elements (PEs) to act autonomously in some significant way. For each autonomy class, we provide examples and illustrate some of its important algorithmic features. We also discuss how each type of autonomy can be simulated on machines without it. We study the addressing autonomous class of machines in greater detail by discussing three algorithms on machines with and without that type of autonomy. A discussion on how processor autonomy appears in algorithms in the literature and what impact they can have in the future machines also is provided.
Starting Page	127
Ending Page	136
Page Count	10
File Format	PDF
ISBN	089791600X
DOI	10.1145/165939.165963
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1993-08-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in