NDLI: A hybrid approach to cyber-physical systems verification

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Biomedical electronics serving as physical environmental and emotional watchdogs

Design of pin-constrained general-purpose digital microfluidic biochips

A semiempirical model for wakeup time estimation in power-gated logic clusters

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Transformer: a functional-driven cycle-accurate multicore simulator

Can EDA combat the rise of electronic counterfeiting?

Physics matters: statistical aging prediction under trapping/detrapping

Tracking appliance usage information in residential settings using off-the-shelf low-frequency meters

Towards fault-tolerant embedded systems with imperfect fault detection

Software controlled cell bit-density to improve NAND flash lifetime

Self-aware computing in the Angstrom processor

Exploring sub-20nm FinFET design with predictive technology models

Symbolic model checking on SystemC designs

Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces

WCET-centric partial instruction cache locking

Algorithms and data structures for fast and good VLSI routing

Making non-volatile nanomagnet logic non-volatile

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A new uncertainty budgeting based method for robust analog/mixed-signal design

X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug

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A hybrid approach to cyber-physical systems verification

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Design challenges for secure implantable medical devices

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Timing ECO optimization using metal-configurable gate-array spare cells

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A hybrid approach to cyber-physical systems verification

Content Provider	ACM Digital Library
Author	Thiele, Lothar Annaswamy, Anuradha Lampka, Kai Chakraborty, Samarjit Kumar, Pratyush Goswami, Dip
Abstract	We propose a performance verification technique for cyber-physical systems that consist of multiple control loops implemented on a distributed architecture. The architectures we consider are fairly generic and arise in domains such as automotive and industrial automation; they are multiple processors or electronic control units (ECUs) communicating over buses like FlexRay and CAN. Current practice involves analyzing the architecture to estimate worst-case end-to-end message delays and using these delays to design the control applications. This involves a significant amount of pessimism since the worst-case delays often occur very rarely. We show how to combine functional analysis techniques with model checking in order to derive a delay-frequency interface that quantifies the interleavings between messages with worst-case delays and those with smaller delays. In other words, we bound the frequency with which control messages might suffer the worst-case delay. We show that such a delay-frequency interface enables us to verify much tigher control performance properties compared to what would be possible with only worst-case delay bounds.
Starting Page	688
Ending Page	696
Page Count	9
File Format	PDF
ISBN	9781450311991
ISSN	85644924
DOI	10.1145/2228360.2228484
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-06-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Stability Timed-automata Real-time calculus Cyber-physical systems Frequency-delay metric
Content Type	Text
Resource Type	Article

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