NDLI: Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry

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Biomedical electronics serving as physical environmental and emotional watchdogs

Design of pin-constrained general-purpose digital microfluidic biochips

A semiempirical model for wakeup time estimation in power-gated logic clusters

A code morphing methodology to automate power analysis countermeasures

Transformer: a functional-driven cycle-accurate multicore simulator

Can EDA combat the rise of electronic counterfeiting?

Physics matters: statistical aging prediction under trapping/detrapping

Tracking appliance usage information in residential settings using off-the-shelf low-frequency meters

Towards fault-tolerant embedded systems with imperfect fault detection

Software controlled cell bit-density to improve NAND flash lifetime

Self-aware computing in the Angstrom processor

Exploring sub-20nm FinFET design with predictive technology models

Symbolic model checking on SystemC designs

Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces

WCET-centric partial instruction cache locking

Algorithms and data structures for fast and good VLSI routing

Making non-volatile nanomagnet logic non-volatile

A methodology for energy-quality tradeoff using imprecise hardware

A new uncertainty budgeting based method for robust analog/mixed-signal design

X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug

Accelerating neuromorphic vision algorithms for recognition

Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology

PowerField: a transient temperature-to-power technique based on Markov random field theory

Static dataflow with access patterns: semantics and analysis

A hybrid approach to cyber-physical systems verification

Design tools for artificial nervous systems

Exploiting die-to-die thermal coupling in 3D IC placement

Removing overhead from high-level interfaces

Accuracy-configurable adder for approximate arithmetic designs

Adaptive power management of on-chip video memory for multiview video coding

Incorrect systems: it's not the problem, it's the solution

Improving gate-level simulation accuracy when unknowns exist

Standard cell sizing for subthreshold operation

Run-time power-down strategies for real-time SDRAM memory controllers

Alternate hammering test for application-specific DRAMs and an industrial case study

Circuit and system design guidelines for ultra-low power sensor nodes

Functional timing analysis made fast and general

A chip-package-board co-design methodology

Yield estimation via multi-cones

Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse

Assessing the performance limits of parallelized near-threshold computing

Accurate process-hotspot detection using critical design rule extraction

Hardware synthesis of recursive functions through partial stream rewriting

CrowdMine: towards crowdsourced human-assisted verification

Communication-aware mapping of KPN applications onto heterogeneous MPSoCs

Integrated biosensors for personalized medicine

Path scheduling on digital microfluidic biochips

Cost-effective power delivery to support per-core voltage domains for power-constrained processors

Security analysis of logic obfuscation

SAGA: SystemC acceleration on GPU architectures

Library-aware resonant clock synthesis (LARCS)

Implementing an FPGA system for real-time intent recognition for prosthetic legs

Steady-state dynamic temperature analysis and reliability optimization for embedded multiprocessor systems

Observational wear leveling: an efficient algorithm for flash memory management

The case for elastic operating system services in fos

Fast nonlinear model order reduction via associated transforms of high-order volterra transfer functions

System verification of concurrent RTL modules by compositional path predicate abstraction

Attackboard: a novel dependency-aware traffic generator for exploring NoC design space

Worst-case execution time analysis for parallel run-time monitoring

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing

mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon

Variability-aware, discrete optimization for analog circuits

Quick detection of difficult bugs for effective post-silicon validation

Statistical memristor modeling and case study in neuromorphic computing

GDRouter: interleaved global routing and detailed routing for ultimate routability

EigenMaps: algorithms for optimal thermal maps extraction and sensor placement on multicore processors

Executing synchronous dataflow graphs on a SPM-based multicore architecture

Reliable computing with ultra-reduced instruction set co-processors

Dynamic river network simulation at large scale

ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement

On the asymptotic costs of multiplexer-based reconfigurability

Recovery-based design for variation-tolerant SoCs

Heterogeneous multi-channel: fine-grained DRAM control for both system performance and power efficiency

On software design for stochastic processors

Automated feature localization for hardware designs using coverage metrics

Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits

Embedding statistical tests for on-chip dynamic voltage and temperature monitoring

Goal-oriented stimulus generation for analog circuits

Design exploration of energy-performance trade-offs for wireless sensor networks

Timing analysis with nonseparable statistical and deterministic variations

Obstacle-avoiding free-assignment routing for flip-chip designs

Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits

Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications

Near-threshold voltage (NTV) design: opportunities and challenges

Improved tangent space based distance metric for accurate lithographic hotspot classification

Chisel: constructing hardware in a Scala embedded language

Extracting design information from natural language specifications

Unrolling and retiming of stream applications onto embedded multicore processors

Design challenges for secure implantable medical devices

Realizing reversible circuits using a new class of quantum gates

A hybrid and adaptive model for predicting register file and SRAM power using a reference design

Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry

Synchronization for hybrid MPSoC full-system simulation

Incremental power grid verification

Statistical design and optimization for adaptive post-silicon tuning of MEMS filters

Considering diagnosis functionality during automatic system-level design of automotive networks

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs

A compiler and runtime for heterogeneous computing

AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits

Equivalence checking for behaviorally synthesized pipelines

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Conforming the runtime inputs for hard real-time embedded systems

Rule agnostic routing by using design fabrics

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture

Near-optimal, dynamic module reconfiguration in a photovoltaic system to combat partial shading effects

Efficient multi-objective synthesis for microwave components based on computational intelligence techniques

Test-data volume optimization for diagnosis

Standard cell routing via boolean satisfiability

An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring

System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC

Identification of recovered ICs using fingerprints from a light-weight on-chip sensor

Humans for EDA and EDA for humans

PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning

SALSA: systematic logic synthesis of approximate circuits

A hybrid NoC design for cache coherence optimization for chip multiprocessors

Joint management of RAM and flash memory with access pattern considerations

What to do about the end of Moore's law, probably!

Path directed abstraction and refinement in SAT-based design debugging

Regaining throughput using completion detection for error-resilient, near-threshold logic

Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices

TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation

Energy harvesting and power management for autonomous sensor nodes

Reversible statistical max/min operation: concept and applications to timing

Clock tree synthesis with methodology of re-use in 3D IC

Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners

Near-threshold operation for power-efficient computing?: it depends...

Simultaneous flare level and flare variation minimization with dummification in EUVL

Specification and synthesis of hardware checkpointing and rollback mechanisms

Material implication in CMOS: a new kind of logic

Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systems

Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors

Coding-based energy minimization for phase change memory

On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction

A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs

Generic low-cost characterization of $V_{th}$ and mobility variations in LTPS TFTs for non-uniformity calibration of active-matrix OLED displays

Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems

Point and discard: a hard-error-tolerant architecture for non-volatile last level caches

The HELIX project: overview and directions

BLAST: efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric Lagrange enabled transient adjoint analysis

Proving correctness of regular expression accelerators

Explicit modeling of control and data for improved NoC router estimation

STM concurrency control for embedded real-time software with tighter time bounds

Hardware realization of BSB recall function using memristor crossbar arrays

Networked architecture for hybrid electrical energy storage systems

Non-uniform multilevel analog routing with matching constraints

Invariance-based concurrent error detection for advanced encryption standard

An efficient algorithm for multi-layer obstacle-avoiding rectilinear Steiner tree construction

Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints

Courteous cache sharing: being nice to others in capacity management

Confidentiality preserving integer programming for global routing

Application of logic synthesis to the understanding and cure of genetic diseases

Structure-aware placement for datapath-intensive circuit designs

Timing ECO optimization using metal-configurable gate-array spare cells

Architecture support for accelerator-rich CMPs

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU

Obtaining and reasoning about good enough software

Checking architectural outputs instruction-by-instruction on acceleration platforms

Process variation in near-threshold wide SIMD architectures

Traffic-aware power optimization for network applications on multicore servers

Small delay testing for TSVs in 3-D ICs

Predicting timing violations through instruction-level path sensitization analysis

Can pin access limit the footprint scaling?

Sparse LU factorization for parallel circuit simulation on GPU

Not so fast my friend: is near-threshold computing the answer for power reduction of wireless devices?

A novel layout decomposition algorithm for triple patterning lithography

Optimizing memory hierarchy allocation with loop transformations for high-level synthesis

Boolean satisfiability using noise based logic

EPIMap: using epimorphism to map applications on CGRAs

EDA for secure and dependable cybercars: challenges and opportunities

DAE2FSM: automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics

Sciduction: combining induction, deduction, and structure for verification and synthesis

Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories

Avoiding game over: bringing design to the next level

GLARE: global and local wiring aware routability evaluation

Early prediction of NBTI effects using RTL source code analysis

A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC

Write performance improvement by hiding R drift latency in phase-change RAM

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method

A metric for layout-friendly microarchitecture optimization in high-level synthesis

Cognitive computing with spin-based neural networks

Instruction scheduling for reliability-aware compilation

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service

Age-based PCM wear leveling with nearly zero search cost

The DAC 2012 routability-driven placement contest and benchmark suite

Generalized SAT-sweeping for post-mapping optimization

Metronome: operating system level performance management via self-adaptive computing

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors

Exploiting narrow-width values for process variation-tolerant 3-D microprocessors

Computer generation of streaming sorting networks

Capacitance of TSVs in 3-D stacked chips a problem?: not for neuromorphic systems!

Compiling for energy efficiency on timing speculative processors

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