NDLI: Translating between itanium and sparc memory consistency models

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Translating between itanium and sparc memory consistency models

Content Provider	ACM Digital Library
Author	Jackson, LillAnne Higham, Lisa
Abstract	Our general goal is to port programs from one multiprocessor architecture to another, while ensuring that each program's semantics remains unchanged. This paper addresses a subset of the problem by determining the relationships between memory consistency models of three Sparc architectures, (TSO, PSO and RMO) and that of the Itanium architecture. First we consider Itanium programs that are constrained to have only one load-type of instruction in {load, load _acquire}, and one store-type of instruction in {store, store_release}. We prove that in three out of four cases, the set of computations of any such program is exactly the set of computations of the "same" program (using only load and store) on one Sparc architecture. In the remaining case the set is nested between two natural sets of Sparc computations.Real Itanium programs, however, use a mixture of load, load acquire, store, store release and memory fence instructions, and real Sparc programs use a variety of barrier instruction as well as load and store instructions. We next show that any mixture of the loadtypes or the store-types (in the case of Itanium) or any barrier instructions (in the case of Sparc) completely destroys the clean and simple similarities between the sets of computations of these systems. Thus (even without considering the additional complications due to register and control dependencies) transforming these more general programs in either direction requires constraining the transformed program substantially more than the original program in order to ensure that no erroneous computations can arise.
Starting Page	170
Ending Page	179
Page Count	10
File Format	PDF
ISBN	1595934529
DOI	10.1145/1148109.1148138
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-07-30
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Program transformations Multiprocessors Sparc Memory consistency models Itanium
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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