NDLI: MODEST: a model for energy estimation under spatio-temporal variability

Please wait, while we are loading the content...

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM

Power-efficient variation-aware photonic on-chip network management

Low-power current-mode transceiver for on-chip bidirectional buses

A 6μw, 100kbps, 3-5ghz, UWB impulse radio transmitter

PEEC based parasitic modeling for power analysis on custom rotary rings

Ultra low power electronics in the next decade

Technology variability and uncertainty implications for power- efficient VLSI systems

Workload-aware neuromorphic design of low-power supply voltage controller

Large-scale battery system modeling and analysis for emerging electric-drive vehicles

Maximum power transfer tracking for a photovoltaic-supercapacitor energy system

Post-silicon power characterization using thermal infrared emissions

Low power logic for statistical inference

Battery management technology for an electric vehicle

Microprocessor power delivery challenges in the Nano-Era

TurboTag: lookup filtering to reduce coherence directory power

PASAP: power aware structured ASIC placement

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs

VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement

Low power branch prediction for embedded application processors

A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opamp

HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs

Distributed DVFS using rationally-related frequencies and discrete voltage levels

Power-efficient directional wireless communication on small form-factor mobile devices

DuraCap: a supercapacitor-based, power-bootstrapping, maximum power point tracking energy-harvesting system

Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives

Resilient microprocessor design for high performance & energy efficiency

Hybrid electrical energy storage systems

Rank-aware cache replacement and write buffering to improve DRAM energy efficiency

Automatic synthesis of near-threshold circuits with fine-grained performance tunability

Custom feedback control: enabling truly scalable on-chip power management for MPSoCs

Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study

Low-power sub-threshold design of secure physical unclonable functions

Reducing variability in chip-multiprocessors with adaptive body biasing

A 5V output voltage boost switching converter with hybrid digital and analog PWM control

Analog circuit shielding routing algorithm based on net classification

NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime

Dynamic thermal management for networked embedded systems under harsh ambient temperature variation

Peak power modeling for data center servers with switched-mode power supplies

Dynamic indexing: concurrent leakage and aging optimization for caches

Computing with stochastic processors: revisiting the correctness contract between software and hardware

Hybrid energy storage system integration for vehicles

An energy efficient cache design using spin torque transfer (STT) RAM

A pareto-algebraic framework for signal power optimization in global routing

STM versus lock-based systems: an energy consumption perspective

Variation aware performance analysis of gain cell embedded DRAMs

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems

Diet SODA: a power-efficient processor for digital cameras

A low-power digitally-programmable variable gain amplifier in 65 nm CMOS

MODEST: a model for energy estimation under spatio-temporal variability

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

PS-BC: power-saving considerations in design of buffer caches serving heterogeneous storage devices

Load-matching adaptive task scheduling for energy efficiency in energy harvesting real-time embedded systems

Models for energy-efficient approximate computing

Wakeup synthesis and its buffered tree construction for power gating circuit designs

Dynamic workload characterization for power efficient scheduling on CMP systems

Low-power dual-element memristor based memory design

3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory

Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach

Replication-aware leakage management in chip multiprocessors with private L2 cache

Leakage minimization using self sensing and thermal management

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection

Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives

Clock network design for ultra-low power applications

Energy efficient implementation of parallel CMOS multipliers with improved compressors

Real-energy: a new framework and a case study to evaluate power-aware real-time scheduling algorithms

A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology

Dynamic thermal management for single and multicore processors under soft thermal constraints

A three-step power-gating turn-on technique for controlling ground bounce noise

Customizing pattern set for test power reduction via improved X-identification and reordering

Analysis and design of ultra low power thermoelectric energy harvesting systems

RAPL: memory power estimation and capping

Energy efficient proactive thermal management in memory subsystem

Power-performance management on an IBM POWER7 server

Energy and thermal-aware video coding via encoder/decoder workload balancing

Tradeoff between energy savings and privacy protection in computation offloading

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

Workload-adaptive process tuning strategy for power-efficient multi-core processors

Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding

MODEST: a model for energy estimation under spatio-temporal variability

Content Provider	ACM Digital Library
Author	Canal, Ramon Ganapathy, Shrikanth Gonzalez, Antonio Rubio, Antonio
Abstract	Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental conditions which makes the problem of energy estimation more dynamic in nature. It is worsened by process induced variations of low level parameters like threshold voltage and channel length. In this paper we present MODEST, a proposal for estimating the static and dynamic energy of caches taking into account spatial variations of physical parameters, temporal changes of supply voltage and environmental factors like temperature. It can be used to estimate the energy of different blocks of a cache based on a combination empirical data and analytical equations. The observed maximum and median error between MODEST and HSPICE energyestimates for 22,500 samples is around 7.8% and 0.5% respectively. As a case study, using MODEST, we propose a two step iterative optimization procedure involving Dual-Vth assignment and standby supply voltage minimization for reclaiming energy-constrained caches. The observed energy reduction is around 50.8% for the most-leaky Cache. A speed-up of 750X over conventional hard-coded implementation for such optimizations is achieved.
Starting Page	129
Ending Page	134
Page Count	6
File Format	PDF
ISBN	9781450301466
DOI	10.1145/1840845.1840873
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-08-18
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Dsm scaling Cache design Spatio-temporal variability
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in