NDLI: Generating concise assertions with complete coverage

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Generating concise assertions with complete coverage

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Generating concise assertions with complete coverage

Content Provider	ACM Digital Library
Author	Liu, Lingyi Vasudevan, Shobha Lin, Chen-Hsuan
Abstract	Assertions are valuable and commonly applied to formal verification and simulation-based verification in IC design flow. Unfortunately, assertion generation is a time-consuming process that depends heavily on human efforts. Some dynamic methods based on simulation and static methods based on structure analysis are proposed to automate assertion generation process. However, dynamic methods cannot guarantee the quality of assertions due to incomplete simulation while static methods might have scalability limits. With the significant advances in Boolean satisfiability (SAT) solving, SAT solving becomes a promising technique to overcome these methods' weaknesses. In this paper, we successfully formulate assertion generation to a SAT problem and use unit assumption to generate concise assertions. Furthermore, we consider input constraints and word level features to generate meaningful and high-readability assertions. Experimental results on SpaceWire, Ethernet, and Floating Point designs show that the generated assertions can always achieve 100% input space coverage.
Starting Page	185
Ending Page	190
Page Count	6
File Format	PDF
ISBN	9781450320320
DOI	10.1145/2483028.2483088
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-05-02
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Word level features Input constraints Complete coverage Assertion generation
Content Type	Text
Resource Type	Article

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