NDLI: A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node

Please wait, while we are loading the content...

A novel statistical and circuit-based technique for counterfeit detection in existing ICs

Harvesting-aware energy management for multicore platforms with hybrid energy storage

Skew-bounded low swing clock tree optimization

An energy-efficient truly all-digital temperature sensor for SoC applications

GPU implementation of a scalable non-linear congruential generator for cryptography applications

Hardware acceleration of retinal blood vasculature segmentation

A novel and improved design of a ternary CNTFET-based cell

A new extension method of retention time for memory cell on dynamic random access memory

Scaling RTL property checking using feasible path analysisand decomposition

Electronics for a greener planet

Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Combating NBTI-induced aging in data caches

Delay model for reconfigurable logic gates based on graphene PN-junctions

On the design of modulo $2^{n}-1$ cubing units

Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs

Multi-port FinFET SRAM design

Low power 3-D stacking multimedia platform with reconfigurable memory architecture

Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstract

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs

Early stage power management for 3D FPGAs considering hierarchical routing resources

Coordinating prefetching and STT-RAM based last-level cache management for multicore systems

Efficient characterization of TSV-to-transistor noise coupling in 3D ICs

Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis

A 191μW BPSK demodulator for data and power telemetry in biomedical implants

Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits

A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware

SIREN: a depth-first search algorithm for the filter design optimization problem

Multi-corner multi-voltage domain clock mesh design

Performance/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional units

Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays

An error tolerant CAM with nand match-line organization

Thermal stress aware 3D-IC statistical static timing analysis

Modeling symmetrical independent gate FinFET using predictive technology model

High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]

Circuit design of a novel adaptable and reliable L1 data cache

A novel intermittent fault Markov model for deep sub-micron processors

A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node

Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above

A portable high-frequency digitally controlled oscillator (DCO)

Translation validation of scheduling in high level synthesis

Custom memory architecture for multi-core implementation of face detection algorithm

Asymmetric-access aware optimization for STT-RAM caches with process variations

A source-synchronous Htree-based network-on-chip

Generating concise assertions with complete coverage

DRMA: dynamically reconfigurable MPSoC architecture

Efficient modulo $2^{n}+1$ multiplication for the idea block cipher

Effect of TSV fabrication technology on power distribution in 3D ICs

A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications

A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm

Physical design exploration of 3D tree-based FPGA architecture

High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy

Virtual register renaming: energy efficient substrate for continual flow pipelines

A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS

LASER: layout-aware analog synthesis environment on laker

A parallel VLSI architecture for Markov chain Monte Carlo based MIMO detection

Efficient transistor-level design of CMOS gates

A compact FPGA-based montgomery multiplier over prime fields

An asymmetric adaptive-precision energy-efficient 3DIC multiplier

An evaluation of an AES implementation protected against EM analysis

Co-optimization of TSV assignment and micro-channel placement for 3D-ICs

PBD: packet buffer DVFs

Lifetime reliability assessment with aging information from low-level sensors

A memory mapping approach for network and controller optimization in parallel interleaver architectures

A hardware-efficient architecture for embedded real-time cascaded support vector machines classification

Post-route refinement for high-frequency PCBs considering meander segment alleviation

Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources

On-chip area-efficient binary sequence storage

Study of ASIC technology impact factors on performance evaluation of SHA-3 candidates

Power gating topologies in TSV based 3D integrated circuits

Timing-constrained replacement using spare cells for design changes

Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector

Rotary traveling wave oscillator frequency division at nanoscale technologies

Reversible synthesis of symmetric boolean functions based on unate decomposition

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in