NDLI: DTPL push down list memory

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DTPL push down list memory

Content Provider	ACM Digital Library
Author	Jauvtis, H. I. Spain, R. J. Marino, M. J.
Abstract	Push down lists (PUDL) or First In Last Out memories have been described for use in multiprocessors. However, in most of these applications, the system's fast access memory is divided in stacks, each program being run in a given stack on a first stack available basis. The push down list is then used to store the program instructions. Very seldom has such a system been described using more than two to six fast access lists. These applications might not justify the use of a special device for the PUDL, making use, instead, of a random access memory section addressed by a pointer address register or counter to keep track of the upper word in the PUDL. There the PUDL storage is only a small fraction of the total fast access storage, and software implementation is more economical than special hardware would be. However, in more sophisticated data processing applications such that language translation, pattern recognition, high speed data acquisition and retrieval, etc., an efficient system organization would result from the use of a central processor working on a multiplicity of programs on a fast interrupt and logic priority basis. The next active program location would depend upon the output from the presently processed instruction. Then the program storage is an important part or even the largest part of the total fast access storage of the system. In this situation, a large number of lists could be required with an access time of the order of one microsecond. If the program instruction lists are stored in a conventional random access memory one pointer register per list would be required and result in an expensive hardware. The pointer could be stored in memory, however, this would result in much increased access time and additional software. A more economical and more efficient implementation of such a multiprogram organization may result from the use a specialized hardware such as a DTPL magnetic thin film Push Down List Memory. The system described here has as an objective the development of a DDPL push down list memory consisting of a set of 128 lists. Each list is 100 words deep with 38 bits per word and thus is implemented by 38 shift registers of 100 bits each. An additional shift register of the same length stores a bottom-of-list (BOL) flag that can be sensed at both ends of the register to deliver an empty or filled list warning signal. Only one magnetic thin film of approximately one inch square area is required for the 38 shift registers constituting one list. The system makes use of a stack of 100 magnetic thin films. Every list is controlled by a conductor that can be selected in a manner similar to that of a word line of a conventional random access memory. The DTPL Push Down List Memory makes use of the controlled propagation of elongated domains of reversed magnetization contained within low coercive force channels imbedded in a magnetic thin film of higher coercive force. This technique of implementation is particularly suited to the construction of bi-directional shift registers with nonvolatile storage and are operable with shifting rates above one megacycle.
Starting Page	491
Ending Page	498
Page Count	8
File Format	PDF
DOI	10.1145/1465482.1465564
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1967-04-18
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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