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| Content Provider | ACM Digital Library |
|---|---|
| Author | McMahon, M. T. Preuss, R. Waxman, R. Borecki, D. |
| Abstract | Integrated Circuit technology has placed many new demands on logic packaging techniques. In order for Large Scale Integration to succeed, additional computer design concepts must be developed. Designers must move away from unit logic and towards dense packages where many integrated circuits are contained in extremely small areas. This implies optimum utilization of input/output connections, since the package size is strongly dependent on the number of I/O's. This paper describes highly-automated computer techniques which may be applied to selected logical graphs to generate the Boolean functions representing the logical graphs. These functions are cataloged into discrete classes. A set of logic functions are then selected from the complete list of discrete classes. Each logical function can cover one or more of the classes in the list. Thus, a small set of logical functions may be utilized to represent a large list of discrete classes obtained from the original partitioning. These functions can be automatically imposed on the original logic graph for evaluation. The automated system is set up to allow rapid evaluation of parameter changes such as function size, and number of function types. The evaluation of functions leads to a set that may be used as the building blocks for implementation of a machine. The designer is free to implement these building blocks in a way that best fits the given technology. This is so because the automated system did not impose any circuit constraints on the logical design. The variable parameters which are included in the system are the number of logical circuits per function, number of I/O's per function, the logic function size allowed, and true and complement available or not available at the output. Reimplementing the machines with the selected function set the packaging parameters that may be varied include the number of functions in a package, the total number of logical circuits in a package, and the number of input and output ports in that assembly. With these freedoms allowed, a designer is in a position to help determine the technology that should be used for his machine design. He can evaluate the amount of redundancy he is willing to allow, and evaluate whether the redundancy actually saves him money or costs him more. He is able to evaluate the effect of the functional density on the wiring complexity since the computer generates the interconnection count between the packaged functions. In this paper, a large high-performance machine and small low-performance machine were analyzed. A function set was chosen for each machine. Results are shown in terms of function usage, logic circuit usage, and wiring complexity. |
| Starting Page | 323 |
| Ending Page | 350 |
| Page Count | 28 |
| File Format | |
| DOI | 10.1145/800195.805942 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1969-08-26 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Content Type | Text |
| Resource Type | Article |
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