NDLI: An educational system of LSI design with free-wares for VDEC

Content Provider	IEEE Xplore Digital Library
Author	Morisawa, F. Kawakami, D. Tanaka, K. Amano, H.
Copyright Year	1999
Description	Author affiliation: Dept. of Comput. Sci., Keio Univ., Yokohama, Japan (Morisawa, F.)
Abstract	VDEC (VLSI Design Education Center), which was developed in 1996, is a Japanese low cost prototyping service organization for LSI circuit development. Universitois can use commercial CAD tools through VDEC for designing LSI chips. However, it is difficult to use such commercial CAD tools in the beginners' classes of designing LSI because of complicated license management in VDEC. A lot of universities in Europe and USA have exploited freeware CAD tools in the beginners' classes, since they are simple, lightweight and easy to use. However, in Japan, such tools cannot be used for design LSI chips for VDEC fabrication. Here, an educational system, which supports designing LSI chips with VDEC using only freeware CAD tools, is developed. This system uses common freeware CAD tools: Alliance, Magic, Irsim and Spice3, and, in order to interface between them, original tools are implemented. For VDEC implementation, Alliance's technology files and libraries, Magic's technology file, and Irsim's library are prepared. As a verification, an 8 bit RISC processor is designed. From the evaluation of execution time, it is shown that this system is able to use in the class of designing LSI by using common PCs.
Starting Page	61
Ending Page	62
File Size	77045
Page Count	2
File Format	PDF
ISBN	0769503128
DOI	10.1109/MSE.1999.787038
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-07-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large scale integration Design automation Libraries Very large scale integration Costs Prototypes Circuits Licenses Educational institutions Europe
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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