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High-speed buffering for variable length operands

Content Provider	ACM Digital Library
Author	Welch, T. A. Tredennick, H. L.
Abstract	Variable word length processing is valuable for data base manipulations, editing functions in time-sharing systems, input-output data formatting, and vector operations, but current computer architectures seldom provide efficient means for manipulating variable length operands. A specialized computer architecture has been proposed to deal with the problems of variable length byte string processing. Operand buffering is a key part of the proposed architecture because the buffer: (1) replaces registers for variable length operands, (2) resolves address precision and operand boundary problems between the main memory and the ALU, and (3) can provide simultaneous access to several operands for faster execution. General observations are made about requirements which constrain memory buffer design and the merits of four memory buffering schemes are discussed. The most suitable of the buffering schemes is discussed in some detail. This scheme provides a separate cache for each of the operands. Hardware costs and timing considerations are given, and show that the multiple-buffer approach to variable word length buffering provides a reasonable cost-performance solution.
Starting Page	205
Ending Page	210
Page Count	6
File Format	PDF
DOI	10.1145/800255.810672
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1977-03-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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