NDLI: A few examples of how to use a symmetrical multi-micro-processor

Content Provider	ACM Digital Library
Author	Mazare, Guy
Abstract	This paper presents an overview of an architecture of a multi-micro-processor architecture in which all processors are equivalent. The structure is characterized by a central memory and several caches, and is designed to avoid incoherent data. A fast mechanism of “subcontracting” between one processor and another is described. The execution of two simple programs under this architecture is studied. The parallel algorithms are described and compared with the original (sequential) algorithms; it is shown that the overhead remains small, few extra memories are necessary and synchronization do not slow down the execution unduly. Furthermore, the locality of the parallel algorithm is compared to that of the sequential algorithm and is found to be less good, but in a reasonable way. As well, an estimation of the cost of the coherence keeping mechanism is given using the difference between the miss ratio of the classical cache and the “coherence keeping cache”, respectively.
Starting Page	57
Ending Page	62
Page Count	6
File Format	PDF
DOI	10.1145/800255.810653
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1977-03-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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A few examples of how to use a symmetrical multi-micro-processor