NDLI: A Programmable Hardware Accelerator for Simulating Dynamical Systems

Please wait, while we are loading the content...

In-Datacenter Performance Analysis of a Tensor Processing Unit

Bespoke Processors for Applications with Ultra-low Area and Power Constraints

Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves

ThermoGater: Thermally-Aware On-Chip Voltage Regulation

Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems

MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation

Quality of Service Support for Fine-Grained Sharing on GPUs

EDDIE: EM-Based Detection of Deviations in Program Execution

LogCA: A High-Level Performance Model for Hardware Accelerators

Hardware Translation Coherence for Virtualized Systems

Language-level persistency

Architectural Support for Server-Side PHP Processing

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware

Viyojit: Decoupling Battery and DRAM Capacities for Battery-Backed DRAM

APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures

ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks

A Programmable Galois Field Processor for the Internet of Things

InvisiMem: Smart Memory Defenses for Memory Bus Side Channel

PowerChief: Intelligent Power Allocation for Multi-Stage Applications to Improve Responsiveness on Power Constrained CMP

Hiding the Long Latency of Persist Barriers Using Speculative Execution

Redundant Memory Array Architecture for Efficient Selective Protection

Accelerating GPU Hardware Transactional Memory with Snapshot Isolation

Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Atacks

Plasticine: A Reconfigurable Architecture For Parallel Paterns

Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations

ShortCut: Architectural Support for Fast Object Access in Scripting Languages

HeteroOS: OS Design for Heterogeneous Memory Management in Datacenter

Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism

Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism

DICE: Compressing DRAM Caches for Bandwidth and Capacity

There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

XPro: A Cross-End Processing Architecture for Data Analytics in Wearables

ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories

CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures

Non-Speculative Load-Load Reordering in TSO

Clank: Architectural Support for Intermittent Computation

Decoupled Affine Computation for SIMT GPUs

Lemonade from Lemons: Harnessing Device Wearout to Create Limited-Use Security Architectures

A Programmable Hardware Accelerator for Simulating Dynamical Systems

Do-It-Yourself Virtual Memory Translation

Understanding and Optimizing Asynchronous Low-Precision Stochastic Gradient Descent

Parallel Automata Processor

The Mondrian Data Engine

Footprint: Regulating Routing Adaptiveness in Networks-on-Chip

MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment

Access Pattern-Aware Cache Management for Improving Data Utilization in GPU

Stream-Dataflow Acceleration

Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB

Jenga: Software-Defined Cache Hierarchies

EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks

The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions

MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability

A Programmable Hardware Accelerator for Simulating Dynamical Systems

Content Provider	ACM Digital Library
Author	Kung, Jaeha Kim, Duckhwan Mukhopadhyay, Saibal Long, Yun
Abstract	The fast and energy-efficient simulation of dynamical systems defined by coupled ordinary/partial differential equations has emerged as an important problem. The accelerated simulation of coupled ODE/PDE is critical for analysis of physical systems as well as computing with dynamical systems. This paper presents a fast and programmable accelerator for simulating dynamical systems. The computing model of the proposed platform is based on multilayer cellular nonlinear network (CeNN) augmented with nonlinear function evaluation engines. The platform can be programmed to accelerate wide classes of ODEs/PDEs by modulating the connectivity within the multilayer CeNN engine. An innovative hardware architecture including data reuse, memory hierarchy, and near-memory processing is designed to accelerate the augmented multilayer CeNN. A dataflow model is presented which is supported by optimized memory hierarchy for efficient function evaluation. The proposed solver is designed and synthesized in 15nm technology for the hardware analysis. The performance is evaluated and compared to GPU nodes when solving wide classes of differential equations and the power consumption is analyzed to show orders of magnitude improvement in energy efficiency.
Starting Page	403
Ending Page	415
Page Count	13
File Format	PDF
ISBN	9781450348928
DOI	10.1145/3079856.3080252
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-06-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Cellular nonlinear network Scientific simulation Hardware accelerator Dynamical systems
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in