NDLI: Cost aware fault tolerant logic synthesis in presence of soft errors

Please wait, while we are loading the content...

A novel design framework for the design of reconfigurable systems based on NoCs

A new physical routing approach for robust bundled signaling on NoC links

8Gb/s capacitive low power and high speed 4-PWAM transceiver design

Stochastic computational models for accurate reliability evaluation of logic circuits

Write activity reduction on flash main memory via smart victim cache

Synthetic biology: from modules to systems

Dominant critical gate identification for power and yield optimization in logic circuits

Online convex optimization-based algorithm for thermal management of MPSoCs

Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors

Graphene tunneling FET and its applications in low-power circuit design

An integrated thermal estimation framework for industrial embedded platforms

A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM

AOP-based high-level power estimation in SystemC

Ordered escape routing via routability-driven pin assignment

Methodology to achieve higher tolerance to delay variations in synchronous circuits

Bus via reduction based on floorplan revising

A low power, variable resolution two-step flash ADC

A multi-level approach to reduce the impact of NBTI on processor functional units

Aging effects of leakage optimizations for caches

Logic synthesis for low power using clock gating and rewiring

Overscaling-friendly timing speculation architectures

Lightweight runtime control flow analysis for adaptive loop caching

Scalable identification of threshold logic functions

Power-efficient, reliable microprocessor architectures: modeling and design methods

Line width optimization for interdigitated power/ground networks

A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes

Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design

Circuit-level NBTI macro-models for collaborative reliability monitoring

Timing-driven variation-aware nonuniform clock mesh synthesis

A low-offset high-speed double-tail dual-rail dynamic latched comparator

Graph theoretic approach for scan cell reordering to minimize peak shift power

Thermal-aware floorplanning exploration for 3D multi-core architectures

Dynamically resizable binary decision diagrams

A model to exploit power-performance efficiency in superscalar processors via structure resizing

Low power nanoscale buffer management for network on chip routers

Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates

Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs

Thermal-aware voltage droop compensation for multi-core architectures

The challenges of implementing fine-grained power gating

Performance-constrained template-driven retargeting for analog and RF layouts

Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems

Scaling power/ground solvers on multi-core with memory bandwidth awareness

Via configurable three-input lookup-tables for structured ASICs

Gating internal nodes to reduce power during scan shift

A mask double patterning technique using litho simulation by wavelet transform

Fast instruction cache modeling for approximate timed HW/SW co-simulation

Thermal-aware compilation for system-on-chip processing architectures

TURBONFS: turbo nand flash search

Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices

A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores

Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance

Performance and energy efficient cache migrationapproach for thermal management in embedded systems

Wirelength-driven force-directed 3D FPGA placement

Enhancing debugging of multiple missing control errors in reversible logic

Bus-pin-aware bus-driven floorplanning

Variation tolerant 9T SRAM cell design

Software adaptation in quality sensitive applications to deal with hardware variability

An effective approach for large scale floorplanning

Clock skew reduction by self-compensating manufacturing variability with on-chip sensors

A linear statistical analysis for full-chip leakage power with spatial correlation

Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory

Challenges and methodologies for efficient power budgeting across the die

Collaborative voltage scaling with online STA and variable-latency datapath

Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers

A novel droplet routing algorithm for digital microfluidic biochips

Algorithm and hardware complexity reduction techniques for k-best sphere decoders

A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths

Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS

A revisit to voltage partitioning problem

On-chip point-of-load voltage regulator for distributed power supplies

Resource-constrained timing-driven link insertion for critical delay reduction

VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications

Boolean satisfiability on a graphics processor

Out-of-order issue logic using sorting networks

Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric

On-chip power supply noise and its implications on timing

Improving the testability and reliability of sequential circuits with invariant logic

Characteristics of MS-CMOS logic in sub-32nm technologies

Deterministic broadside test generation for transition path delay faults

A self-adaptive scheduler for asymmetric multi-cores

A delay measurement method using a shrinking clock signal

Context-aware TLB preloading for interference reduction in embedded multi-tasked systems

Energy-efficient redundant execution for chip multiprocessors

Design of self correcting radiation hardened digital circuits using decoupled ground bus

On-die sensors for measuring process and environmental variations in integrated circuits

A novel multi-objective instruction synthesis flow for application-specific instruction set processors

Cost aware fault tolerant logic synthesis in presence of soft errors

Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects

Design of embedded MRAM macros for memory-in-logic applications

Topology impact on the room temperature performance of THz-range ballistic deflection transistors

Performance assessment of analog circuits with carbon nanotube FET (CNFET)

Read-out schemes for a CNTFET-based crossbar memory

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in