NDLI: A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems

Please wait, while we are loading the content...

From dataflow analysis basics to the programming of ASICs

Compiler-Directed Data Locality Optimization in MATLAB

A Lightweight Design Space Exploration and Optimization Language

Cross-Layer Reliability Modeling and Optimization: Compiler and Run-Time System Interactions

Scalable DFA Compilation for High-Performance Regular-Expression Matching

An Extensible Platform Description Language Supporting Retargetable Toolchains and Adaptive Execution

A Design Framework for Mapping Vectorized Synchronous Dataflow Graphs onto CPU-GPU Platforms

Exploring Single Source Shortest Path Parallelization on Shared Memory Accelerators

CSDFa: A Model for Exploiting the Trade-Off between Data and Pipeline Parallelism

In-Place Update in a Dataflow Synchronous Language: A Retiming-Enabled Language Experiment

Introducing MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems

HAPI: An Event-Driven Simulator for Real-Time Multiprocessor Systems

Vectorization in PyPy's Tracing Just-In-Time Compiler

Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems

Practical Challenges of ILP-based SPM Allocation Optimizations

Determining Performance Boundaries on High-Level System Specifications

Compositional Temporal Analysis Method for Fixed Priority Pre-emptive Scheduled Modal Stream Processing Applications

Automatic Generation of Thread Communication Graphs from SystemC Source Code

RDBG: a Reactive Programs Extensible Debugger

Energy-Optimized Static Scheduling for Many-Cores with Task Parallelization, DVFS and Core Consolidation

Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms

Sporadic Task Handling in Time-Triggered Systems

A Task-Level Monitoring Framework for Multi-Processor Platforms

Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs

Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors

Studying the Impact of Bit Switching on CPU Energy

A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems

Content Provider	ACM Digital Library
Author	Wild, Thomas Wagner, Philipp Ramaswamy, Ramesh Li, Lin Herkersdorf, Andreas Mayer, Albrecht
Abstract	As the complexity of multicore SoCs increases, more potential system issues are arising. Hardware-related configuration issues are becoming more complicated owing to the introduction of more cores and various complex peripherals. Considering the complexity of multicore programming, consultation of the main source of guidance, i.e. the user manual, is not an efficient approach to identify such problems. Improper hardware-related configurations could lead to either functional or performance issues. Some of these issues are even subtle and hard to detect. Therefore, a rule-based validation methodology is proposed to deal with hardware-related configuration issues in an efficient and reliable way. Hardware trace is applied in this methodology to detect issues even before symptoms appear. The method directly observes the register accesses and detects bugs based on trace data. It is independent of the application as long as they are run on the given platform, which means the same method implementation could be applied to any applications on the same platform. In this paper, an initial proof-of-concept for the proposed methodology has been implemented and demonstrated on the Infineon TC29 device.
Starting Page	180
Ending Page	189
Page Count	10
File Format	PDF
ISBN	9781450343206
DOI	10.1145/2906363.2906377
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-05-23
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Trace Embedded systems Hardware configurations Soc Debug
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Validation and robustness assessment of an automotive system

Validation of SoC Firmware-Hardware Flows: Challenges and Solution Directions

An embedded infrastructure of debug and trace interface for the DSP platform

Embedded software debug and test: Needs and requirements for innovations in debugging

Functional Debug Techniques for Embedded Systems

An embedded infrastructure of debug and trace interface for the DSP platform

5a-4 a debug probe for concurrently debugging multiple embedded cores and inter-core transactions in noc-based systems.

On-chip memory size configuration of SOC system based on real-time constraints

ISTA: An embedded architecture for post-silicon validation in processors

A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems

Similar Documents

Validation and robustness assessment of an automotive system

Validation of SoC Firmware-Hardware Flows: Challenges and Solution Directions

An embedded infrastructure of debug and trace interface for the DSP platform

Embedded software debug and test: Needs and requirements for innovations in debugging

Functional Debug Techniques for Embedded Systems

An embedded infrastructure of debug and trace interface for the DSP platform

5a-4 a debug probe for concurrently debugging multiple embedded cores and inter-core transactions in noc-based systems.

On-chip memory size configuration of SOC system based on real-time constraints

ISTA: An embedded architecture for post-silicon validation in processors

A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems