NDLI: A comparative study of arbitration algorithms for the Alpha 21364 pipelined router

Please wait, while we are loading the content...

Transactional lock-free execution of lock-based programs

Automatically characterizing large scale program behavior

Maté: a tiny virtual machine for sensor networks

ECOSystem: managing energy as a first class operating system resource

Design and evaluation of compiler algorithms for pre-execution

Dynamic dead-instruction detection and elimination

Increasing web server throughput with network interface data caching

A stateless, content-directed data prefetching mechanism

Keynote address: Sensor network research: emerging challenges for architecture, systems, and languages

Speculative synchronization: applying thread-level speculation to explicitly parallel applications

Bytecode fetch optimization for a Java interpreter

Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet

Cool-Mem: combining statically speculative memory accessing with selective address translation for energy efficiency

Compiler optimization of scalar value communication between speculative threads

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

Programming language optimizations for modular router configurations

A stream compiler for communication-exposed architectures

Temporally silent stores

Understanding and improving operating system effects in control flow prediction

Enabling trusted software integrity

Joint local and global hardware adaptations for energy

Enhancing software reliability with speculative threads

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router

Evolving RPC for active storage

Mondrian memory protection

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router

Content Provider	ACM Digital Library
Author	Bannon, Peter Webb, David Emer, Joel Silla, Federico Lang, Steve Mukherjee, Shubhendu S.
Abstract	Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.
Starting Page	223
Ending Page	234
Page Count	12
File Format	PDF
ISBN	1581135742
DOI	10.1145/605397.605421
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-10-05
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router (CARN, Vol. 30, Issue. 5)

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router (SIGP, Vol. 37, Issue. 10)

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router (OPSR, Vol. 36, Issue. 5)

A study of the alpha 21364 processor.

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers (2003)

Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor

Pre-silicon verification of the Alpha 21364 microprocessor error handling system

A Hybrid Wave-Pipelined Network Router

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers (2002)

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router

Similar Documents

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router (CARN, Vol. 30, Issue. 5)

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router (SIGP, Vol. 37, Issue. 10)

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router (OPSR, Vol. 36, Issue. 5)

A study of the alpha 21364 processor.

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers (2003)

Performance analysis of the Alpha 21364-based HP GS1280 multiprocessor

Pre-silicon verification of the Alpha 21364 microprocessor error handling system

A Hybrid Wave-Pipelined Network Router

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers (2002)

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router