NDLI: On the use of reset to increase the testability of interconnected finite-state machines

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Organizing and Program Committee

Technical Program Committee

Keynote Speakers

Welcome Message

Best Paper Award

List of Reviewers

RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems

Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications

Interface Timing Verification with Delay Correlation Using Constraint Logic Programming

Sequential Circuit Test Generation Using Dynamic State Traversal

MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits

New Static Compaction Techniques of Test Sequences for Sequential Circuits

A Methodology for Designing Continuous-Time Sigma-Delta Modulators

A CMOS Low Voltage, High Gain Op-Amp

High-Level Synthesis of Analog Sensor Interface Front-Ends

Structural BIST Insertion Using Behavioral Test Analysis

On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs

Cellular Automata for Generating Deterministic Test Sequences

Fast Controllers for Data Dominated Applications

Random Benchmark Circuits with Controlled Attributes

Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and Resynthesis

Generation of the HDL-A-Model of a Micromembrane from Its Finite-Element-Description

Microsystem Design Using Simulator Coupling

Modeling and Simulation of Electromechanical Transducers in Microsystems Using an Analogue Hardware Description Language

Delay Management for Programmable Video Signal Processors

Hierarchical Scheduling and Allocation of Multirate Systems on Heterogeneous Multiprocessors

Retargetable Generation of Code Selectors from HDL Processor Models

An RTL Methodology to Enable Low Overhead Combinational Testing

A Controller Testability Analysis and Enhancement Technique

Analyzing Testability from Behavioral to RT Level

Fast and Efficient Construction of BDDs by Reordering Based Synthesis

Verification and Synthesis of Counters Based on Symbolic Techniques

Using MTBDDs for Discrete Timed Symbolic Model Checking

Analysis of 3D Conjugate Heat Transfers in Electronics

Smart Sensor System Application: An Integrated Compass

Automatic Transfer of Parametric FEM Models into CAD-Layout Formats for Top-Down Design of Microsystems

Highly Scalable Parallel Parametrizable Architecture of the Motion Estimator

Design and Implementation of a Coprocessor for Cryptography Applications

On the Way to the 2.5 Gbits/s ATM Network ATM Multiplexer Demultiplexer ASIC

Solving Graph Optimization Problems with ZBDDs

Minimizing ROBDD Sizes of Incompletely Specified Boolean Functions by Exploiting Strong Symmetries

Connection Errors Location and Correction in Combinational Circuits

Shaping a VLSI Wire to Minimize Elmore Delay

Inductance Analysis of On-Chip Interconnects

Cartesian Multipole Based Numerical Integration for 3D Capacitance Extraction

Networked CAD Systems

CCII+ Current Conveyor Based BIC Monitor for IDDQ Testing of Complex CMOS Circuits

Deep Sub-Micron IDDQ Testing: Issues and Solutions

A Production-Oriented Measurement Method for Fast and Exhaustive Iddq Tests

Library Mapping for Memories

Architectural Exploration and Optimization for Counter Based Hardware Address Generation

RTL Synthesis with Physical and Controller Information

Two-way partitioning based on direction vector

Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic

A gridless multi-layer router for standard cell circuits using CTM cells

Deep Submicron CAD

A Programmable Boundary Scan Technique for Board-level, Parallel Functional Duplex March Testing of Word-Oriented Multiport Static RAMs

Fault-secure shifter design: results and implementations

High-Speed C-Testable Systolic Array Design for Galois-Field InversionChih-Tsun Huang and Cheng-Wen Wu

Efficient and accurate testing of analog-to-digital converters using oscillation-test method

Built-in self-test methodology for A/D converters

Reconfigurable data converter as a building block for mixed-signal test

Multichip Packages for Consumer Applications

VHDL extensions for complex transmission line simulation

Acceleration of Behavioral Simulation on Simulation Specific Machines

Exploiting temporal independence in distributed preemptive circuit simulation

Analogue layout generation by World Wide Web server-based agents

A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC's

An Algorithm for Numerical Reference Generation in Symbolic Analysis of Large Analog Circuits

Adaptive least mean square behavioral power modeling

Fast power loss calculation for digital static CMOS circuits

Monte-Carlo Approach for Power Estimation in Sequential Circuits

Hybrid symbolic-explicit techniques for the graph coloring problem

A constructive approach towards correctness of synthesis-application within retiming

A symbolic core approach to the formal verification of integrated mixed-mode applications

A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code

Testing scheme for IC's clocks

A Totally Self-checking 1-out-of-3 Code Error Indicator

Cone Based Clustering for List Scheduling Algorithms

Register Synthesis for Speculative Computation

Multidimensional periodic scheduling: a solution approach

Multi-thread graph: a system model for real-time embedded software synthesis

PCC: a modeling technique for mixed control/data flow systems

Procedure cloning: a transformation for improved system-level functional partitioning

A fault diagnosis methodology for the UltraSPARC/sup TM/-I microprocessor

Improved diagnosis of realistic interconnect shorts

On improving genetic optimization based test generation

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks

Low power FSM design using Huffman-style encoding

Improving the Accuracy of Support-Set Finding Method for Power Estimation of Combinational Circuits

Practical concurrent ASIC and system design and verification

A Methodology for Hardware Architecture Trade-off at Different Levels of Abstraction

Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications

Testability of 2-level AND/EXOR circuits

On the use of reset to increase the testability of interconnected finite-state machines

A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs

On-chip analog output response compaction

A new quality estimation methodology for mixed-signal and analogue ICs

Compact structural test generation for analog macros

Accurate high level datapath power estimation

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

Internal power modelling and minimization in CMOS inverters

A new field programmable system-on-a-chip for mixed signal integration

PROPHID: a data-driven multi-processor architecture for high-performance DSP

ReCode: the design and re-design of the instruction codes for embedded instruction-set processors

A real-time smart sensor system for visual motion estimation

Full custom chip set for high speed serial communications up to 2.48 Gbit/s

An asynchronous architecture for digital signal processors

Test synthesis for DC test of switched-capacitors circuits

SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells

Design of Oscillation-Based Test Structures for Active RC Filters

Using Constraint Logic Programming in Memory Synthesis for General Purpose Computers

Optimal Scheduling for Fast Systolic Array Implementations

Scheduling using mixed arithmetic: an ILP formulation

Performance verification using partial evaluation and interval analysis

Design and Verification of the Sequential Systems Automata Using Temporal Logic Specifications

Application independent module generation in analog layouts

A scheme for multiple on-chip signature checking for embedded SRAMs

Design of Partially Parallel Scan Chain

March LA: a test for linked memory faults

The input pattern fault model and its application

A monolithic off-chip IDDQ monitor

Extension of the Boundary-Scan Architecture and New Idea of BIST for More Effective Testing and Self-Testing of Interconnections

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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