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Content Provider | ACM Digital Library |
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Author | Liu, Le-Chin Eugene Sechen, C. |
Abstract | We present a chip-level global router based on a new, more accurate global routing model for the multi-layer macro-cell technology. The routing model uses a 3-dimensional mixed directed/undirected routing graph, which accurately models the multi-layer routing problem. However the complexity of the routing graph challenges previous route-generating algorithms. Generating the routes is to search for the Steiner minimum trees for the nets, which is an NP-hard problem. We developed an improved Steiner tree heuristic algorithm suitable for large routing graphs and able to generate high quality Steiner tree routing. Tested on industrial circuits, our algorithm yields comparable results while having dramatically lower time and space complexities than the leading heuristics. While minimizing the wire length, our global router can also minimize the number of vias or solve the routing resource congestion problems. |
File Format | |
ISBN | 0818677864 |
Language | English |
Publisher | Association for Computing Machinery (ACM) |
Publisher Date | 1997-03-17 |
Access Restriction | Subscribed |
Subject Keyword | Multilayer macro-cell technology Large routing graphs Vias minimisation Routing resource congestion problems Chip-level global routing Graph-based steiner tree heuristic Multilayer routing problem Np-hard problem Steiner tree heuristic algorithm Space complexity 3d mixed directed/undirected routing graph Network routing Global routing model Wire length minimisation Steiner minimum trees Time complexity |
Content Type | Text |
Resource Type | Article |
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