NDLI: InvisiFence: performance-transparent memory ordering in conventional multiprocessors

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InvisiFence: performance-transparent memory ordering in conventional multiprocessors

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InvisiFence: performance-transparent memory ordering in conventional multiprocessors

Content Provider	ACM Digital Library
Author	Wenisch, Thomas F. Blundell, Colin Martin, Milo M.K.
Abstract	A multiprocessor's memory consistency model imposes ordering constraints among loads, stores, atomic operations, and memory fences. Even for consistency models that relax ordering among loads and stores, ordering constraints still induce significant performance penalties due to atomic operations and memory ordering fences. Several prior proposals reduce the performance penalty of strongly ordered models using post-retirement speculation, but these designs either (1) maintain speculative state at a per-store granularity, causing storage requirements to grow proportionally to speculation depth, or (2) employ distributed global commit arbitration using unconventional chunk-based invalidation mechanisms. In this paper we propose InvisiFence, an approach for implementing memory ordering based on post-retirement speculation that avoids these concerns. InvisiFence leverages minimalistic mechanisms for post-retirement speculation proposed in other contexts to (1) track speculative state efficiently at block-granularity with dedicated storage requirements independent of speculation depth, (2) provide fast commit by avoiding explicit commit arbitration, and (3) operate under a conventional invalidation-based cache coherence protocol. InvisiFence supports both modes of operation found in prior work: speculating only when necessary to minimize the risk of rollback-inducing violations or speculating continuously to decouple consistency enforcement from the processor core. Overall, InvisiFence requires approximately one kilobyte of additional state to transform a conventional multiprocessor into one that provides performance-transparent memory ordering, fences, and atomic operations.
Starting Page	233
Ending Page	244
Page Count	12
File Format	PDF
ISBN	9781605585260
DOI	10.1145/1555754.1555785
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-06-20
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Parallel programming Memory consistency
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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InvisiFence:performance-transparent memory ordering in conventional multiprocessors

InvisiFence: Performance-Transparent Memory Ordering in Conventional Multiprocessors (2009)

Volition: scalable and precise sequential consistency violation detection

Midway: shared memory parallel programming with entry consistency for distributed memory multiprocessors (1991).

WeeFence: toward making fences free in TSO

Retrospective: memory consistency and event ordering in scalable shared-memory multiprocessors

Memory consistency and event ordering in scalable shared-memory multiprocessors ( selected papers )

Memory consistency and event ordering in scalable shared-memory multiprocessors ( ISCA '90 )

Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors (1990)

InvisiFence: performance-transparent memory ordering in conventional multiprocessors

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