NDLI: Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09)

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Architecting phase change memory as a scalable dram alternative

Dynamic MIPS rate stabilization in out-of-order processors

Spatio-temporal memory streaming

Architectural core salvaging in a multi-core processor for hard-error tolerance

AnySP: anytime anywhere anyway signal processing

Multi-execution: multicore caching for data-similar executions

A case for bufferless routing in on-chip networks

InvisiFence: performance-transparent memory ordering in conventional multiprocessors

Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices

Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors

A case for an interleaving constrained shared-memory multi-processor

End-to-end performance forecasting: finding bottlenecks before they happen

Performance and power of cache-based reconfigurable computing

Firefly: illuminating future network-on-chip with nanophotonics

Dynamic performance tuning for speculative threads

Ten ways to waste a parallel computer

A durable and energy efficient main memory using phase change memory technology

Hardware support for WCET analysis of hard real-time multicore systems

Stream chaining: exploiting multiple levels of correlation in data prefetching

End-to-end register data-flow continuous self-test

Rigel: an architecture and scalable programming interface for a 1000-core accelerator

PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches

Application-aware deadlock-free oblivious routing

Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors

Disaggregated memory for expansion and sharing in blade servers

Thread motion: fine-grained power management for multi-core systems

SigRace: signature-based data race detection

Scaling the bandwidth wall: challenges in and avenues for CMP scaling

A memory system design framework: creating smart memories

Phastlane: a rapid transit optical routing network

Boosting single-thread performance in multi-core systems through fine-grain multi-threading

Internet-scale service infrastructure efficiency

Scalable high performance main memory system using phase-change memory technology

Memory mapped ECC: low-cost error protection for last level caches

An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness

Reactive NUCA: near-optimal block placement and replication in distributed caches

Indirect adaptive routing on large scale interconnection networks

The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization

Temperature-constrained power control for chip multiprocessors with online model estimation

ECMon: exposing cache events for monitoring

A fault tolerant, area efficient architecture for Shor's factoring algorithm

Flexible reference-counting-based hardware acceleration for garbage collection

Achieving predictable performance through better memory controller placement in many-core CMPs

Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor

Hybrid cache architecture with disparate memory technologies

Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09)

Content Provider	ACM Digital Library
Editor	Gurumurthi, Sudhanva Keckler, Steve Barroso, Luiz André Burger, Doug Witchel, Emmett Das, Chita R. Eeckhout, Lieven Dally, Bill Chiou, Derek González, Antonio Qureshi, Moinuddin K. Mercaldi-Kim, Martha Martinez, José Jouppi, Norm Torrellas, Josep Olukotun, Kunle Falsafi, Babak
Copyright Year	2009
Abstract	It is a pleasure to introduce the ISCA 2009 program representing the state-of-the-art in computer architecture research. Serving as ISCA Program Chair gave me a front row seat to observe the vitality of the research in our field, and the dedication of the members of the organizing committee, program committee and reviewers. It has been an honor to work with such an incredibly talented team. In selecting the program committee (PC) my primary goal was to form a group of recognized experts with interests that matched the predicted mix of submission topics. Achieving balances between industrial and academic representation, and between experience and new talent was also important. This year's PC had roughly 40% membership from industry, 57% of the members had served in one of the last three ISCA PCs and 32% were serving in the ISCA PC for the first time. More significantly, over 94% of the papers had at least two reviewers rating themselves as experts in the subject area, indicating very good topic area coverage. The selection process was heavily influenced by what I learned serving on Mark Hill's (ISCA'05) and Brad Calder's (ISCA'07) PCs. I am especially grateful to them for their generosity of advice throughout. Reviewing was double blind, with typically four PC and one non-PC review per paper. I made all the reviewing assignments except for submissions I had conflicts with, which were managed by Josep Torrellas -- in total we had 1028 reviews. Authors were invited to read the reviews and to submit a short rebuttal, after which reviewers were then asked to re-score all papers. Re-scoring after rebuttals affected over 70% of all submissions, and caused five eventually accepted papers to improve their final rank by more than thirty positions. I believe that the combination of rebuttals and re-scoring improved the quality of our evaluation process significantly. Recognizing that sometimes the external reviewer is the most knowledgeable for a given article, I invited them to participate in the rebuttals and re-scoring phases, and asked the PC member leading the discussion for each paper to be the advocate for the external reviewer. I also used a Review Committee, an idea introduced by Steve Blackburn at ISMM'08, which consisted of experts recruited before the submissions deadline who agreed to review between four and six submissions. Besides greatly simplifying the assignment of non-PC reviews, the Review Committee gave me more opportunities for expert reviewer overlap across similar papers, which helped process calibration. In the PC meeting we discussed papers which had a majority of scores in the accept range, plus every paper that any PC member felt that we should discuss. I explicitly did not set a maximum number of papers to accept and did not publish the list of accepted papers until after the meeting was finished. The PC worked with no breaks and through lunch from 8:00am until 5:30pm, showing remarkable stamina, focus and professionalism. I am pleased that we have been able to continue the recent ISCA trend of a larger program, with 43 papers accepted out of 210 submissions (12 out of 45 among submissions with PC authors), and I encourage future committees to continue to strive for a large and more diverse program.
ISBN	9781605585260
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-06-20
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

Sl.	Authority	Responsibilities	Communication Details
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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