NDLI: Can CAD meet the VLSI design problems of the 80's

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A two-dimensional placement algorithm for the master slice LSI layout problem

A hierarchical placement procedure with a simple blocking scheme

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IC specification language

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Electron beam lithography

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Hierarchical modeling and simulation in VISTA

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The complete VLSI design system

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An introduction to the N. mPc design environment

The N. mPc system description facility

The N.mPc runtime environment

An evaluation of the N. mPc design environment

Can C.A.D. meet the VLSI design problems of the 80's?(Panel Discussion)

Will Disign tools catch up to VLSI design

VLSI - a design challenge

VLSI design methodology the problem of the 80's for microprocessor design

CAD system for VLSI

Can CAD meet the VLSI design problems of the 80's?

Can CAD meet the VLSI design problems of the 80's

Computer hardware description languages and their applications

Developments in computer simulation of gate level physical logic

Can CAD meet the VLSI design problems of the 80's

Content Provider	ACM Digital Library
Author	Hightower, David
Abstract	The technology of the 80's will permit 106 transistors to be placed on one IC, but what kind of function will the device serve? It is unlikely that a random logic circuit of 106 transistors would be designed, let alone realized in hardware. Such an IC would probably be 5” on a side because the total interconnect length (manual or automatic) grows exponentially (approximately .62 N1.226) with the number of devices. This effect can be offset somewhat using multilayer routing, but cannot be satisfactorily overcome because the performance of the circuit will degrade with exponential growth of the average interconnect length. But since the technology allows 106 devices per chip, we have to take advantage of it. Given that the design of such a device will be very difficult and time consuming, it is unlikely that very many of them will be designed. Instead, only a few will be designed, and these will be general purpose devices. The customer will provide the ROM program, and the microelectronics house will supply the programmed part. A typical part will have lots of memory, say 64K of RAM; various other standard design elements, e.g., PLA's, Registers, etc.; and lots of ROM containing the control logic. This type of device could be standardized, and the vendor would only have to insert the ROM code and possibly add one or more layers of interconnect to complete the customization process. We could call such a device a Multi-purpose Super Component, or MSP. With the MSP, layout cycle time is traded for program development time. A study of the economics involved suggests that considerable effort can be expended to assure ROM code correctness without offsetting the benefit of not having to design a new hardware part.
Starting Page	552
Ending Page	553
Page Count	2
File Format	PDF
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1979-06-25
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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