NDLI: “Views of a vendor” (Position Paper)

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A min-cut placement algorithm for general cell assemblies based on a graph representation

A two-dimensional placement algorithm for the master slice LSI layout problem

A hierarchical placement procedure with a simple blocking scheme

Placement algorithm by partitioning for optimum rectangular placement

Incremental processing applied to Steinberg's placement procedure

The use of color and 3-D temporal and spatial data management techniques in computer-aided design

A low cost satellite for fast interactive graphics in a time-sharing environment

Concepts of a microcomputer design language

The MIMOLA design system a computer aided digital processor design method

The MIMOLA design system: Detailed description of the software system

Instruction set processor specifications for simulation, evaluation, and synthesis

The CMU design automation system: An example of automated data path design

Unified Shapes Checker - a checking tool for LSI

Circuit simulation and timing verification based on MOS/LSI mask information

LSI layout checking using bipolar device recognition technique

CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI

A new circuit placement program for FET chips

An experimental input system of hand-drawn logic circuit diagram for LSI CAD

Automatic pipe routing and material take-off system for chemical plant

Stonewalls: Experiments in intelligent drafting

DRAW3D: Time sharing graphic interaction using a device-space buffer

Computer simulation of foliage shading in building energy loads

Multiple fault diagnosis in combinational networks

TMEAS, a testability measurement program

Testing of MOS combinational networks a procedure for efficient fault simulation and test generation

Behavioral-level test development

Generation of hazard free tests using the D-algorithm in a timing accurate system for logic and deductive fault simulation

Designers Workbench—efficient and economical design aids

A procedure for checking the topological consistency of a 2-D or 3-D finite element mesh

Computer Aided Ship Design and numerically controlled production of towing tank models

Automation of manufacturing planning, shop loading and work measurement in an engineering job shop environment

A partial solution to fitting large parametric surfaces in computer-aided design systems

Macrosimulation with Quasi-general Symbolic FET Macromodel and Functional Latency

Methods of modelling digital devices for logic simulation

Digital logic simulation at the gate and functional level

A hybrid scheduling technique for hierarchical logic simulators or “Close Encounters of the Simulated Kind”

Efficient simulation of AHPL

SILOG: A practical tool for large digital network simulation

SABLE: A tool for generating structured, multi-level simulations

Symbolic simulation for correct machine design

Optimal layout of CMOS functional arrays

The minimum width routing of A 2-row 2-layer polycell-layout

MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks

Introduction to silicon compilation

IC specification language

Bristle Blocks: A silicon compiler

Silicon compilation-a hierarchical use of PLAs

A software system for Automated Placement And Wiring of LSI chips

Dynamic design rule checking in an interactive printed circuit editor

PC board layout techniques

The real world of design automation - part II or adapting to the joys of madness (Panel Session)

“Views of a vendor” (Position Paper)

Design Automation concerns (Position Paper)

Future of design automation (Position Paper)

Moving a D.A. system from development to production (Position Paper)

Design Automation philosophies (Position Paper)

Design verification based on functional abstraction

Design and verification of large-scale computers by using DDL

Logic verification system for very large computers using LSI's

The application of program verification techniques to hardware verification

Cost effective data entry techniques for design automation

Electron beam lithography

Hughes S&CG custom LSI layouts - 'we did it our way'

A Computer-Aided Design data base

Hierarchical modeling and simulation in VISTA

A placement capability based on partitioning

A design aids data base for digital components

Descriptive databases in some design/manufacturing environments

Component library for an integratel DA system

The design of an efficient data base to support an interactive LSI layout system

The complete VLSI design system

Topological analysis for VLSI circuits

Placement algorithms for arbitrarily shaped blocks

New algorithms for grid-less routing of high density printed circuit boards

A “lookahead” router for multilayer printed wiring boards

An application of branch and bound method to automatic printed circuit board routing

An interactive routing program with On-line clean-up of sketched routes

An interactive layout system of analog printed wiring boards

An introduction to the N. mPc design environment

The N. mPc system description facility

The N.mPc runtime environment

An evaluation of the N. mPc design environment

Can C.A.D. meet the VLSI design problems of the 80's?(Panel Discussion)

Will Disign tools catch up to VLSI design

VLSI - a design challenge

VLSI design methodology the problem of the 80's for microprocessor design

CAD system for VLSI

Can CAD meet the VLSI design problems of the 80's?

Can CAD meet the VLSI design problems of the 80's

Computer hardware description languages and their applications

Developments in computer simulation of gate level physical logic

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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