NDLI: A low power VLIW processor generation method by means of extracting non-redundant activation conditions

Please wait, while we are loading the content...

Beyond gaming: programming the PLAYSTATION®3 cell architecture for cost-effective parallel processing

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC

Synchronization after design refinements with sensitive delay elements

Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

Combined approach to system level performance analysis of embedded systems

Energy efficient co-scheduling in dynamically reconfigurable systems

Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems

Fresh air: the emerging landscape of design for networked embedded systems

Locality optimization in wireless applications

Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip

Complex task activation schemes in system level performance analysis

ESL design and HW/SW co-verification of high-end software defined radio platforms

Performance modeling for early analysis of multi-core systems

A low power VLIW processor generation method by means of extracting non-redundant activation conditions

Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors

Automotive networks: are new busses and gateways the answer or just another challenge?

Complexity challenges towards 4th generation communication solutions

Compiling code accelerators for FPGAs

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

Embedded software development on top of transaction-level models

Secure FPGA circuits using controlled placement and routing

Event-based re-training of statistical contention models for heterogeneous multiprocessors

Thread warping: a framework for dynamic synthesis of thread accelerators

Temperature-aware processor frequency assignment for MPSoCs using convex optimization

A code-generator generator for multi-output instructions

Performance and resource optimization of NoC router architecture for master and slave IP cores

Improved response time analysis of tasks scheduled under preemptive Round-Robin

Smart driver for power reduction in next generation bistable electrophoretic display technology

Bridging gap between simulation and spreadsheet study

Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems

Predator: a predictable SDRAM memory controller

Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules

Pointer re-coding for creating definitive MPSoC models

A smart random code injection to mask power analysis based side channel attacks

HySim: a fast simulation framework for embedded software development

HW/SW co-design for Esterel processing

Three-dimensional multiprocessor system-on-chip thermal optimization

Influence of procedure cloning on WCET prediction

Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels

Probabilistic performance risk analysis at system-level

On the impact of manufacturing process variations on the lifetime of sensor networks

Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions

Reliable multiprocessor system-on-chip synthesis

Performance improvement of block based NAND flash translation layer

Ensuring secure program execution in multiprocessor embedded systems: a case study

A computational reflection mechanism to support platform debugging in SystemC

Compile-time decided instruction cache locking using worst-case execution paths

A data protection unit for NoC-based architectures

A low power VLIW processor generation method by means of extracting non-redundant activation conditions

Content Provider	ACM Digital Library
Author	Sakanushi, Keishi Iwato, Hirofumi Imai, Masaharu Takeuchi, Yoshinori
Abstract	This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is important for the best power reduction by clock gating to create control signals that can completely shut off redundant clock supplies for registers. In order to generate the control signals automatically, the proposed method utilizes high-level architecture information called Micro-Operation Descriptions, which describes a VLIW processor architecture. Exploiting the Micro-Operation Descriptions in a VLIW processor generation process, the proposed method automatically extracts the non-redundant activation conditions that can control clock gating to supply the minimum clocks to the pipeline registers. Using the non-redundant activation condition extraction, the proposed method achieves short calculation time and low area overhead; the proposed method can be applied to VLIW processor generation. Experimental results show that the VLIW processor generated with proposed method achieves power reduction about 60% compared to the non-clock-gated VLIW processor, and about 35% compared to the VLIW processor that is applied clock gating by PowerCompiler with negligible area overhead.
Starting Page	227
Ending Page	232
Page Count	6
File Format	PDF
ISBN	9781595938244
DOI	10.1145/1289816.1289872
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-09-30
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Clock gating Asip Vliw processor Low power
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in