NDLI: A data protection unit for NoC-based architectures

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A data protection unit for NoC-based architectures

A data protection unit for NoC-based architectures

Content Provider	ACM Digital Library
Author	Lukovic, Slobodan Fiorin, Leandro Silvano, Cristina Palermo, Gianluca
Abstract	Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights (none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.
Starting Page	167
Ending Page	172
Page Count	6
File Format	PDF
ISBN	9781595938244
DOI	10.1145/1289816.1289858
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-09-30
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Network-on-chip (noc) Embedded systems Multiprocessor system-on-chip (mpsoc) Data protection Security
Content Type	Text
Resource Type	Article

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