NDLI: High performance dense linear algebra on a spatially distributed processor

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High performance dense linear algebra on a spatially distributed processor

Content Provider	ACM Digital Library
Author	Goto, Kazushige Robatmili, Behnam Keckler, Stephen W. Burger, Doug Diamond, Jeffrey R. van de Geijn, Robert
Abstract	As technology trends have limited the performance scaling of conventional processors, industry and academic research has turned to parallel architectures on a single chip, including distributed uniprocessors and multicore chips. This paper examines how to extend the archtypical operation of dense linear algebra, matrix multiply, to an emerging class of uniprocessor architectures characterized by a large number of independent functional units, register banks, and cache banks connected by a 2-D on-chip network. We extend the well known algorithm for matrix multiplication by Goto to this spatially distributed class of uniprocessor and describe the optimizations of the innermost kernel, a systolic-like algorithm running on a general purpose uniprocessor. The resulting implementation yields the first demonstration of high-performance in an application executing on the TRIPS processor hardware, a next-generation distributed processor core. We show that such processors are indeed capable of substantial improvements in single threaded performance provided their spatial topography is taken into account.
Starting Page	63
Ending Page	72
Page Count	10
File Format	PDF
ISBN	9781595937957
DOI	10.1145/1345206.1345218
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-02-20
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Matrix multiply Instruction level parallelism Hybrid dataflow Tile based architecture Grid processors Gotoblas Dense linear algebra On-chip networks
Content Type	Text
Resource Type	Article

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