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| Content Provider | ACM Digital Library |
|---|---|
| Author | Su, Stephen Y. H. |
| Abstract | An interactive design automation system is presented which, after complete implementation, will allow the designer to check the determinacy and dead locks of the system before implementation. The design can be evaluated at various levels and modified interactively. The designer enters his design specification using either graphical representation or design language statements. The translator accepts the input and produces a data base for both the simulator and the logic synthesizer. The synthesizer accepts information from the function library of integrated circuits and designer-defined modules as well as the design constraints such as fan-in, fan-out and cost, and design goals set by the designer and produces a logic diagram. Simulators are utilized for design verification and performance evaluation at system and gate levels. |
| Starting Page | 253 |
| Ending Page | 261 |
| Page Count | 9 |
| File Format | |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1973-06-25 |
| Access Restriction | Subscribed |
| Content Type | Text |
| Resource Type | Article |
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