NDLI: Automatic generation of diagnostic programs for TOSBAC

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Automatic generation of diagnostic programs for TOSBAC - 5400/150

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Automatic generation of diagnostic programs for TOSBAC - 5400/150

Content Provider	ACM Digital Library
Author	Miyoshi, Akira
Abstract	Because the computer is playing an increasing important role in the community, its availability has become an essential and inherent factor. The availability of a computer is defined by the formula: availability &equil; 100×MTBF/(MTBF + MTTR) (%) where MTBF &equil; mean time between failures MTTR &equil; mean time to repair. The techniques for components such as MSI, LSI and IC and for manufacturing have drastically improved the MTBF during the relatively short history of the computer. However, no special systematic care has been taken to improve the MTTR, except the introduction of testing programs which verify functional operations of computer units. When a testing program encounters an irregular operation, it is not an easy task for a maintainer to find a failing component. As a matter of fact, much training is needed in this area for maintainers and customer engineers. Recently, a hardware-oriented fault diagnostic program was developed for medium-and large-scale computers. The main purpose of this program is to localize a failing component within some replaceable components. The diagnostic program is generated automatically, with considerations given to the logical or functional behavior of the computer components. This paper describes some phases of the fault diagnostic program for TOSBAC - 5400/150. The TOSBAC - 5400/150 is a microprogrammed computer with self-diagnosis capabilities. The design goal is to limit MTTR to less than 30 minutes and the diagnostic resolution is within three chips. The replaceable unit is an IC chip. The test pattern generator (TPG) was developed to generate the fault diagnostic program. The TPG is a total program system which comprises the logic extractor, the test generator, the test evaluator, the fault dictionary builder and the test editor. The test editor is the interface program of the TPG and the diagnostic hardware of the TOSBAC - 5400/150. (See Figure 1 for a schematic view of the TPG). Replacement of a part of the test editor makes it possible to generate a fault diagnostic program for a microprogrammable processor other than the TOSBAC - 5400/150.
Starting Page	213
Ending Page	221
Page Count	9
File Format	PDF
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1973-06-25
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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