NDLI: Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization

Content Provider	ACM Digital Library
Author	Katagiri, Hisaaki Higashino, Teruo Kitajima, Akira Taniguchi, Kenichi Yasumoto, Keiichi
Abstract	In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of multi-way synchronization enables simple and comprehensible specifications of recent communication protocols which frequently use complicated mechanisms such as mutual exclusion and dynamic job assignment, the proposed model is expected to reduce development cost in designing/developing such protocols. We implement specifications described in the model so that EFSMs work synchronously with the same clock, and that the synchronization mechanism for checking executability of each tuple of synchronizing transitions is implemented as a combinational logic circuit. Through some experiments, we have confirmed that the proposed technique can synthesize hardware circuits with relatively good performances for practical use.
Starting Page	762
Ending Page	767
Page Count	6
File Format	PDF
ISBN	1581131879
DOI	10.1145/337292.337771
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2000-06-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Mutli-way synchronization Communication protocols High-level synthesis Lotos Concurrent efsms
Content Type	Text
Resource Type	Article

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Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization