NDLI: Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor

Content Provider	ACM Digital Library
Author	Yen, Jen-Tien Yin, Qichao Richard
Abstract	Multiprocessing (MP) design verification has been one of the bottlenecks for high performance microprocessor design projects. The problem is getting worse as the design complexity increases and more cache structures are integrated into one single chip. The challenges that MP verification faces today include: huge chip/system simulation model sizes, long simulation cycles, relative inefficiency of the simulation tools compared to uniprocessor, and so on. To solve these challenging problems, we developed a new methodology and simulation flow for an upcoming design in Motorola's G4 generation of microprocessors, MPC74XX1. The key strategy of this methodology was to start MP verification as early as the design implementation started. The same methodology/tool set were first developed for MP verification at the unit level, then reused at the multiple-unit level, and eventually reused at the chip/system level. In this paper, we will present the details of this methodology, and demonstrate why it is effective and efficient in detecting the majority of the MP functional defects at an early stage of the design phase.
Starting Page	718
Ending Page	723
Page Count	6
File Format	PDF
ISBN	1581131879
DOI	10.1145/337292.337755
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2000-06-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor