NDLI: Tradeoffs in supporting two page sizes

Please wait, while we are loading the content...

A performance study of memory consistency models

Lazy release consistency for software distributed shared memory

Hiding memory latency using dynamic scheduling in shared-memory multiprocessors

Effects of building blocks on the performance of super-scalar architecture

Limits of control flow on parallelism

The expandable split window paradigm for exploiting fine-grain parallelsim

Towards a shared-memory massively parallel multiprocessor

Comparative performance evaluation of cache-coherent NUMA and COMA architectures

The DASH prototype: implementation and performance

Performance evaluation of a decoded instruction cache for variable instruction-length computers

A simulation based study of TLB performance

Alternative implementations of two-level adaptive branch prediction

An elementary processor architecture with simultaneous instruction issuing from multiple threads

Thread-based programming for the EM-4 hybrid dataflow machine

T: a multithreaded massively parallel architecture

Adjustable block size coherent caches

Performance optimization of pipelined primary cache

Cache replacement with dynamic exclusion

Processor coupling: integrating compile time and runtime scheduling for parallelism

Improved multithreading techniques for hiding communication latency in multiprocessors

Instruction-level parallelism in Prolog: analysis and architectural support

Memory latency effects in decoupled architectures with a single data memory module

Interleaved parallel schemes: improving memory throughput on supercomputers

Active messages: a mechanism for integrated communication and computation

Planar-adaptive routing: low-cost adaptive networks for multiprocessors

The turn model for adaptive routing

Low-latency message communication support for the AP1000

Futurebus+ as an I/O bus: profile B

A study of I/O system organizations

Comparison of sparing alternatives for disk arrays

Monitoring program behaviour on SUPRENUM

Dynamic dependency analysis of ordinary programs

An analysis of loop latency in dataflow execution

A novel cache design for vector processing

Increasing the number of strides for conflict-free vector access

Evaluation of the WM architecture

The impact of communication locality on large-scale multiprocessor performance

Performance of the SCI ring

Tradeoffs in supporting two page sizes

OPAC (abstract): A floating-point coprocessor dedicated to compute-bound kernels

Parallel electro-optical rule-based system for fast execution of expert systems (abstract)

A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation (abstract)

The time-constrained barrier synchronizer and its applications in parallel systems (abstract)

Performance evaluation of disk subsystems

Architecture of a graphics processor (abstract)

Enhancing boosting with semantic register in a superscalar processor (abstract)

Prefetch unit for vector operations on scalar computers (abstract)

Memory management support for tiled array organization (abstract)

Data path issues in a highly concurrent machine (abstract)

Seamless - a latency-tolerant RISC-based multiprocessor architecture (abstract)

Performance of multiple-bus multiprocssor under non-uniform memory reference model (abstract)

Performance improvement for vector pipeline multiprocessor systems using a disordered execution model(abstract)

A class of prefetch schemes for on-chip data caches

Synthesis of application-specific heterogeneous multiprocessor systems (abstract)

Pipelining and bypassing in a VLIW processor (abstract)

A partitioned translation lookaside buffer approach to reducing address bandwith (abstract)

Architectural and implementation tradeoffs in the design of multiple-context processors (abstract)

Expanded delta networks for very large parallel computers

Implications of hierarchical N-body methods for multiprocessor architecture

Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches

Directory-based cache coherency protocol for a ring-connected multiprocessor-array

Analysis of multithreaded microprocessors under multiprogramming

Cache write generate for high performance parallel processing

Integrated computer architecture development system

Tradeoffs in supporting two page sizes

Content Provider	ACM Digital Library
Author	Kong, Shing Patterson, David A. Talluri, Madhusudhan Hill, Mark D.
Abstract	As computer system main memories get larger and processor cycles-per-instruction (CPIs) get smaller, the time spent in handling translation lookaside buffer (TLB) misses could become a performance bottleneck. We explore relieving this bottleneck by (a) increasing the page size and (b) supporting two page sizes.We discuss how to build a TLB to support two page sizes and examine both alternatives experimentally with a dozen uniprogrammed, user-mode traces for the SPARC architecture. Our results show that increasing the page size to 32KB causes both a significant increase in average working set size (e.g., 60%) and a significant reduction in the TLB's contribution to CPI, CPITLB, (namely a factor of eight) compared to using 4KB pages. Results for using two page sizes, 4KB and 32KB pages, on the other hand, show a small increase in working set size (about 10%) and variable decrease in CPITLB, (from negligible to as good as found with the 32KB page size). CPITLB when using two page sizes is consistently better for fully associative TLBs than for set-associative ones.Our results are preliminary, however, since (a) our traces do not include multiprogramming or operating system behavior, and (b) our page-size assignment policy may not reflect a real operating system's policy.
Starting Page	415
Ending Page	424
Page Count	10
File Format	PDF
ISBN	0897915097
DOI	10.1145/139669.140406
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1992-05-19
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in