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  1. Proceedings of the 6th International Workshop on Performance Modeling, Benchmarking, and Simulation of High Performance Computing Systems (PMBS '15)
  2. Examining recent many-core architectures and programming models using SHOC
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Performance evaluation of the IBM POWER8 architecture to support computational neuroscientific application using morphologically detailed neurons
Performance analysis of OpenMP on a GPU using a CORAL proxy application
Examining recent many-core architectures and programming models using SHOC
Automatic loop kernel analysis and performance modeling with Kerncraft
Techniques for modeling large-scale HPC I/O workloads
Characterizing node orderings for improved performance
Simulating stencil-based application on future Xeon Phi processor
ARMv8 micro-architectural design space exploration for high performance computing using fractional factorial
Guided profiling for auto-tuning array layouts on GPUs

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Examining recent many-core architectures and programming models using SHOC

Content Provider ACM Digital Library
Author Young, Jeffrey Meredith, Jeremy S. Lopez, M. Graham Roth, Philip C. Vetter, Jeffrey S. Horton, Mitchel
Abstract The Scalable HeterOgeneous Computing (SHOC) benchmark suite was released in 2010 as a tool to evaluate the stability and performance of emerging heterogeneous architectures and to compare different programming models for compute devices used in those architectures. Since then, high-performance computing (HPC) system architectures have increasingly incorporated both discrete and fused multi-core and many-core processors. The TOP500 list illustrates this trend: heterogeneous systems grew from a 3.4% to 18.0% share of the list between June 2010 and June 2015. Not only are there more heterogeneous systems on the TOP500 list today, those machines are responsible for a disproportionately large percentage of list's aggregate performance: as of June 2015, the performance share for heterogeneous systems has grown to 33.7%. Part of this shift toward heterogeneous architectures has stemmed from new products in the hardware accelerator market, such as Intel's Xeon Phi coprocessor, and improvements in the approaches for programming such accelerators. Existing approaches such as CUDA and OpenCL have become more powerful and easy to use, and directive-based programming models such as OpenACC, OpenMP 4.0, and Intel's Language Extensions for Offload (LEO) are rapidly gaining user acceptance. The benefits of these hardware and software advances are not limited to HPC; other problem domains such as "big data" are reaping the rewards also. The original SHOC benchmarks had adequate support for CUDA and OpenCL for graphics processing units, but did not support more recent programming models and devices. We extended SHOC to support evaluation of recent heterogeneous architectures and programming models such as OpenACC and LEO, and we added new benchmarks to increase SHOC's application domain coverage. In this paper, we describe our modifications to the stock SHOC distribution and present several examples of using our augmented version of SHOC for evaluation of recent heterogeneous architectures and programming models.
Starting Page 1
Ending Page 12
Page Count 12
File Format PDF
ISBN 9781450340090
DOI 10.1145/2832087.2832090
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2015-11-15
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Accelerators Benchmarking Performance
Content Type Text
Resource Type Article
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