NDLI: A european perspective on supercomputing

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A european perspective on supercomputing

The roadrunner project and the importance of energy efficiency on the road to exascale computing

Computing outside the box

Implementation of a wide-angle lens distortion correction algorithm on the cell broadband engine

Zero-content augmented caches

OhHelp: a scalable domain-decomposing dynamic load balancing for particle-in-cell simulations

Fast memory snapshot for concurrent programmingwithout synchronization

Parametric multi-level tiling of imperfectly nested loops

Efficient high performance collective communication for the cell blade

Fast and scalable list ranking on the GPU

Creating artificial global history to improve branch prediction accuracy

A graph based approach for MPI deadlock detection

FTL design exploration in reconfigurable high-performance SSD for server applications

Single-particle 3d reconstruction from cryo-electron microscopy images on GPU

Combining thread level speculation helper threads and runahead execution

EpiFast: a fast algorithm for large scale realistic epidemic simulations on distributed memory systems

Adagio: making DVS practical for complex HPC applications

MPI collective communications on the blue gene/p supercomputer: algorithms and optimizations

High-performance regular expression scanning on the Cell/B.E. processor

Dynamic cache clustering for chip multiprocessors

Pattern-based sparse matrix representation for memory-efficient SMVM kernels

QuakeTM: parallelizing a complex sequential application using transactional memory

Dynamic parallelization of single-threaded binary programs using speculative slicing

Practice of parallelizing network applications on multi-core architectures

Tuned and wildly asynchronous stencil kernels for hybrid CPU/GPU systems

Exploring pattern-aware routing in generalized fat tree networks

Maximizing MPI point-to-point communication performance on RDMA-enabled clusters with customized protocols

/scratch as a cache: rethinking HPC center scratch storage

How GPUs can outperform ASICs for fast LDPC decoding

Limited early value communication to improve performance of transactional memory

Using many-core hardware to correlate radio astronomy signals

A comprehensive power-performance model for NoCs with multi-flit channel buffers

TransMetric: architecture independent workload characterization for transactional memory benchmarks

Computer generation of fast fourier transforms for the cell broadband engine

Less reused filter: improving l2 cache performance via filtering less reused lines

Dynamic topology aware load balancing algorithms for molecular dynamics applications

Refereeing conflicts in hardware transactional memory

Synchronization optimizations for efficient execution on multi-cores

Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design

Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs

Understanding the interconnection network of SpiNNaker

MPI-aware compiler optimizations for improving communication-computation overlap

P-Code: a new RAID-6 code with optimal properties

A translation system for enabling data mining applications on GPUs

A parallel levenberg-marquardt algorithm

Rate-based QoS techniques for cache/memory in CMP platforms

Cancellation of loads that return zero using zero-value caches

DBDB: optimizing DMATransfer for the cell be architecture

Divide-and-conquer: a bubble replacement for low level caches

Chunking parallel loops in the presence of synchronization

Virtualization polling engine (VPE): using dedicated CPU cores to accelerate I/O virtualization

Evaluating high performance communication: a power perspective

R-ADMAD: high reliability provision for large-scale de-duplication archival storage systems

Auto-vectorization through code generation for stream processing applications

Subdomain communication to increase scalability in large-scale scientific applications

Access map pattern matching for data cache prefetch

Prediction-based power estimation and scheduling for CMPs

Design of a novel SIMD architecture by fusing operations and registers

Thrifty interconnection network for HPC systems

Performance modeling for DFT algorithms in FFTW

PARSEC: hardware profiling of emerging workloads for CMP design

Approximate kernel matrix computation on GPUs forlarge scale learning applications

Dynamic task set partitioning based on balancing memory requirements to reduce power consumption

High-performance CUDA kernel execution on FPGAs

Load balancing using work-stealing for pipeline parallelism in emerging applications

Prefetch optimizations on large-scale applications via parameter value prediction

Designing multi-socket systems using silicon photonics

An infrastructure for scalable and portable parallel programs for computational chemistry

A european perspective on supercomputing

Content Provider	ACM Digital Library
Author	Valero, Mateo
Abstract	Massive computing systems will be needed to maintain competitiveness in all areas of science, engineering and business, to provide both management efficiency and computing capability. From a systems management perspective, massive installations offer an efficient platform for resource sharing and service-oriented cloud computing; from a capability perspective, they allow unprecedented performance for supercomputing applications. With top supercomputing systems reaching the PetaFlop barrier, the next challenge is to devise technology to reach, and applications to take advantage of, ExaFlop performance. Multicore chips are already here but will grow in the next decade to several hundred cores. Although these chips will be used for general-purpose computing, they will be the tera-device components of future exascale systems. Europe is aware of the importance of having a well-structured supercomputing infrastructure, as well as the need to exchange experiences and know-how across the Union. Infrastructure projects such as the current DEISA (Distributed European Infrastructure for Supercomputing Applications) or the future PRACE (Partnership for Advanced Computing in Europe) aim at setting up such coordinated resources. PRACE, in particular, will create a world-class pan-European high performance computing service and infrastructure, managed as a single European entity. The service will include five superior supercomputing centers, strengthened by regional and national centers, working in collaboration through grid technologies. The BSC-CNS is the Spanish representative, one of five principal partners in the project (the others being Germany, France, UK and the Netherlands). The principal partner countries have agreed to contribute more to the PRACE budget, and to host the tier-0 machines which will form part of the distributed infrastructure. Having hit the power wall, the computing market is now undergoing a shaky era of dispersion, where many kinds of multicore alternatives are being proposed as the way to develop chips with ever increasing performance capabilities. In this time of confusion we have built a tight Gordian knot, where excitement at the potential performance shown by different hardware platforms is counteracted by the fear of wasted effort in targeting applications to each and every one of those platforms. We believe that the programming model is the key component that should break the knot. With increased scale, hierarchical levels of granularity should be considered, providing the programmer with an abstract model that will be mapped to the different target platforms by their specific runtimes. Asynchrony, decoupling between logical and physical resources of all types (cores, memory, etc.), load balancing, fault tolerance, and actual understanding of the behavior of our systems are issues that will have to be addressed and supported when targeting exascale performance. Holistic approaches with a global vision for the design of such systems should coordinate experience and techniques at all levels, from application to programming model design, runtime implementation, and architecture, both at the node and interconnect level. The talk will first describe how the BSC and the Spanish distributed infrastructure of computers (RES) around it was set up, and discuss experiences with its operation. Then some of the European activities will be described, finishing with the BSC's vision on the major issues in designing and using the upcoming systems of the ExaFlop era.
Starting Page	1
Ending Page	1
Page Count	1
File Format	PDF
ISBN	9781605584980
DOI	10.1145/1542275.1542277
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-06-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multicore architectures Supercomputing grids Exascale computing Programming models Supercomputing infrastructure Exaflop
Content Type	Text
Resource Type	Article

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