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  1. Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH '08)
  2. Spike-timing-dependent learning in memristive nanodevices
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Spike-timing-dependent learning in memristive nanodevices

Content Provider ACM Digital Library
Author Snider, Greg S.
Abstract The neuromorphic paradigm is attractive for nanoscale computation because of its massive parallelism, potential scalability, and inherent defect-, fault-, and failure-tolerance. We show how to implement timing-based learning laws, such as spike-timing-dependent plasticity (STDP), in simple, memristive nanodevices, such as those constructed from certain metal oxides. Such nano-scale “synapses” can be combined with CMOS “neurons” to create neuromorphic hardware several orders of magnitude denser than is possible in conventional CMOS. The key ideas are: (1) to factor out two synaptic state variables to pre- and post-synaptic neurons; and (2) to separate computational communication from learning by time-division multiplexing of pulse-width-modulated signals through synapses. This approach offers the advantages of: better control over power dissipation; fewer constraints on the design of memristive materials used for nanoscale synapses; learning dynamics can be dynamically turned on or off (e.g. by attentional priming mechanisms communicated extra-synaptically); greater control over the precise form and timing of the STDP equations; the ability to implement a variety of other learning laws besides STDP; better circuit diversity since the approach allows different learning laws to be implemented in different areas of a single chip using the same memristive material for all synapses.
Starting Page 85
Ending Page 92
Page Count 8
File Format PDF
ISBN 9781424425525
DOI 10.1109/NANOARCH.2008.4585796
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2008-06-12
Access Restriction Subscribed
Content Type Text
Resource Type Article
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