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  1. Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH '08)
  2. On brain-inspired connectivity and hybrid network topologies
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System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors
Online test and fault-tolerance for nanoelectronic programmable logic arrays
Assessing random dynamical network architectures for nanoelectronics
Locality aware redundancy allocation in nanoelectronic systems
A DSP nanosystem with defect tolerance
A voterless strategy for defect-tolerant nano-architectures
Defect tolerance in QCA-based PLAs
On brain-inspired connectivity and hybrid network topologies
Reconfigurable BDD based quantum circuits
Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits
Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis
Spike-timing-dependent learning in memristive nanodevices
rFGA: CMOS-nano hybrid FPGA using RRAM components

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On brain-inspired connectivity and hybrid network topologies

Content Provider ACM Digital Library
Author Kelly, Peter M. Beiu, Valeriu Madappuram, Basheer A. M. McDaid, Liam J.
Abstract This paper starts from very fresh analyses comparing brain’s connectivity with those of well-known network topologies, based on the latest interpretation of Rent’s rule. Those analyses have revealed how close the brain comes to the latest Rent’s rule averages. On the other hand, all the known network topologies seems to fall short of being strong contenders for mimicking the brain. That is why this paper performs a detailed Rent-based (top-down) connectivity analysis of many two-level hybrid network topologies. This analysis aims to identify those two-level hybrid network topologies which are able to closely mimic brain’s connectivity. The ranges of granularity (as given by the total number of gates and the number of processors) where this mimicking is happening are identified. These results should have implications for the design of networks(-on-chip) and for the burgeoning field of multi/many-core processors (in the short to medium term), as well as for investigations on future nano-architectures (in the long run). Complementary results using a bottom-up approach have also been obtained, and will be mentioned.
Starting Page 54
Ending Page 61
Page Count 8
File Format PDF
ISBN 9781424425525
DOI 10.1109/NANOARCH.2008.4585792
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2008-06-12
Access Restriction Subscribed
Content Type Text
Resource Type Article
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