NDLI: LUCAS: latency-adaptive unified cluster assignment and instruction scheduling

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LUCAS: latency-adaptive unified cluster assignment and instruction scheduling

Content Provider	ACM Digital Library
Author	Porpodas, Vasileios Cintra, Marcelo
Abstract	Clustered VLIW architectures are statically scheduled wide-issue architectures that combine the advantages of wide-issue processors along with the power and frequency scalability of clustered designs. Being statically scheduled, they require that the decision of mapping instructions to clusters be done by the compiler. State-of-the-art code generation for such architectures combines cluster-assignment and instruction scheduling in a single unified pass. The performance of the generated code, however, is very susceptible to the inter-cluster communication latency. This is due to the nature of the two clustering heuristics used. One is aggressive and works well for low inter-cluster latencies, while the other is more conservative and works well only for high latencies. In this paper we propose LUCAS, a novel unified cluster-assignment and instruction-scheduling algorithm that adapts to the inter-cluster latency better than the existing state-of-the-art schemes. LUCAS is a hybrid scheme that performs fine-grain switching between the two state-of-the art clustering heuristics, leading to better scheduling than either of them. It generates better performing code for a wide range of inter-cluster latency values.
Starting Page	45
Ending Page	54
Page Count	10
File Format	PDF
ISBN	9781450320856
DOI	10.1145/2465554.2465565
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-06-20
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Cluster assignment Instruction scheduling Clustered vliw
Content Type	Text
Resource Type	Article

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