NDLI: Architectural support for register allocation in the presence of aliasing

Content Provider	ACM Digital Library
Author	Heggy, Ben Soffa, Mary Lou
Abstract	High performance computer architectures use registers to provide high speed access to data operands, to provide short names for operands, and to reduce memory traffic for accesses to these operands. The possibility of aliasing in a program segment reduces the quality of code that a compiler can produce by necessitating that memory and register copies of variables that have been allocated to registers be kept consistent. A hardware support mechanism is presented that permits all classes of data objects, including dynamically allocated objects and array elements, to be held in registers without consideration of possible aliases and without requiring that the generated code maintain consistency between register and memory copies of variables. Use of this approach permits programs to benefit from the speed advantages and reduced memory traffic associated with register storage, obviates the need to collect aliasing information for use in register allocation, and reduces instruction traffic by eliminating code used solely to maintain register-memory consistency. The support hardware can be implemented using known hardware technology and without increasing the cycle time of the processor.
Starting Page	730
Ending Page	739
Page Count	10
File Format	PDF
ISBN	0897914120
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1990-11-12
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Architectural support for register allocation in the presence of aliasing