NDLI: Parametric Timing Analysis (LCTES '01)

Please wait, while we are loading the content...

An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors

Hybrid Run-time Power Management Technique for Real-time Embedded System with Voltage Scalable Processor

Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems

Combining Global Code and Data Compaction

Register Allocation for Banked Register File

Loop Transformations for Architectures with Partitioned Register Banks

ENSEMBLE: A Communication Layer for Embedded Multi-Processor Systems

Embedded Control Systems Development with Giotto

A tool for simulation and fast prototyping of embedded control systems

MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems

Parametric Timing Analysis

Interval-Based Analysis of Software Processes

Automatic Accurate Live Memory Analysis for Garbage-Collected Languages

Generating Decision Trees for Decoding Binaries

Dealing with Hardware in Embedded Software: A General Framework Based on the Devil Language

Morphable Cache Architectures: Potential Benefits

Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture

ILP-based Instruction Scheduling for IA-64

C Compiler Design for an Industrial Network Processor

A Dynamic Programming Approach to Optimal Integrated Code Generation

Stuck in the Middle: Challenges and Trends in Optimizing Middleware

Optimizing Component Interaction

Using Cohort Scheduling to Enhance Server Performance (Extended Abstract)

Middleware For Building Adaptive Systems Via Configuration

Designing and Optimizing a Scalable CORBA Notification Service

Issues in the Design of Adaptive Middleware Load Balancing

Evaluating and Optimizing Thread Pool Strategies for Real-Time CORBA

Designing an Efficient and Scalable Server-side Asynchrony Model for CORBA

Integration of QoS-Enabled Distributed Object Computing Middleware for Developing Next-Generation Distributed Application

Language and Compiler Support for Adaptive Distributed Applications

Parametric Timing Analysis (LCTES '01)

Content Provider	ACM Digital Library
Author	Mueller, Frank Whalley, David Vivancos, Emilio Healy, Christopher
Abstract	Embedded systems often have real-time constraints. Traditional timing analysis statically determines the maximum execution time of a task or a program in a real-time system. These systems typically depend on the worst-case execution time of tasks in order to make static scheduling decisions so that tasks can meet their deadlines. Static determination of worst-case execution times imposes numerous restrictions on real-time programs, which include that the maximum number of iterations of each loop must be known statically. These restrictions can significantly limit the class of programs that would be suitable for a real-time embedded system. This paper describes work-in-progress that uses static timing analysis to aid in making dynamic scheduling decisions. For instance, different algorithms with varying levels of accuracy may be selected based on the algorithm's predicted worst-case execution time and the time allotted for the task. We represent the worst-case execution time of a function or a loop as a formula, where the unknown values affecting the execution time are parameterized. This parametric timing analysis produces formulas that can then be quickly evaluated at run-time so dynamic scheduling decisions can be made with little overhead. Benefits of this work include expanding the class of applications that can be used in a real-time system, improving the accuracy of dynamic scheduling decisions, and more effective utilization of system resources.
Starting Page	88
Ending Page	93
Page Count	6
File Format	PDF
ISBN	1581134258
DOI	10.1145/384197.384230
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-08-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in