NDLI logo
  • Content
  • Similar Resources
  • Metadata
  • Cite This
  • Log-in
  • Fullscreen
Log-in
Do not have an account? Register Now
Forgot your password? Account recovery
  1. Proceedings of the eighth international conference on Architectural support for programming languages and operating systems (ASPLOS VIII)
  2. Compiler-controlled memory
Loading...

Please wait, while we are loading the content...

Compiler-controlled memory
Segregating heap objects by reference behavior and lifetime
Schedule-independent storage mapping for loops
An empirical analysis of instruction repetition
Space-time scheduling of instruction-level parallelism on a raw machine
Data speculation support for a chip multiprocessor
VISA: Netstation's virtual Internet SCSI adapter
Active disks: programming model, algorithms and evaluation
A cost-effective, high-bandwidth storage architecture
Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy
Dependence based prefetching for linked data structures
Performance counters and state sharing annotations: a unified approach to thread locality
Cache-conscious data placement
An out-of-order execution technique for runtime binary translators
Overlapping execution with transfer using non-strict execution for mobile programs
Variable length path branch prediction
Performance isolation: sharing and isolation in shared-memory multiprocessors
UTLB: a mechanism for address translation on network interfaces
Locality-aware request distribution in cluster-based network servers
Investigating optimal local memory performance
Precise miss analysis for program transformations with caches of arbitrary associativity
Capturing dynamic memory reference behavior with adaptive cache topology
Accelerating multi-media processing by implementing memoing in multiplication and division units
Value speculation scheduling for high performance processors
An empirical study of decentralized ILP execution models
Fast out-of-order processor simulation using memoization
A look at several memory management units, TLB-refill mechanisms, and page table organizations
Performance of database workloads on shared-memory systems with out-of-order processors

Similar Documents

...
Compiler-Controlled Memory (1998)

Proceeding

...
Compiler-Controlled Memory (1998)

Proceeding

...
Compiler-Controlled Memory (1998)

Article

...
Enabling programmer-controlled combined memory consistency for compiler optimization.

...
SMLNJ : Intel x 86 back end Compiler Controlled Memory

Article

...
Enabling Programmer-controlled Combined Memory Consistency for Compiler Optimization

Article

...
Overcoming Limitations Of Prefetching In Multiprocessors By Compiler-Initiated Coherence Action

Article

...
A GPGPU compiler for memory optimization and parallelism management

Article

...
There is nothing wrong with out-of-thin-air: compiler optimization and memory models

Article

Compiler-controlled memory

Content Provider ACM Digital Library
Author Cooper, Keith D. Harvey, Timothy J.
Abstract Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a. reasonable level of success. The primary limit on the compiler's ability to improve memory behavior is its imperfect knowledge about the run-time behavior of the program. The compiler cannot completely predict runtime access patterns.There is an exception to this rule. During the register allocation phase, the compiler often must insert substantial amounts of spill code; that is, instructions that move values from registers to memory and back again. Because the compiler itself inserts these memory instructions, it has more knowledge about them than other memory operations in the program.Spill-code operations are disjoint from the memory manipulations required by the semantics of the program being compiled, and, indeed, the two can interfere in the cache. This paper proposes a hardware solution to the problem of increased spill costs---a small compiler-controlled memory (CCM) to hold spilled values. This small random-access memory can (and should) be placed in a distinct address space from the main memory hierarchy. The compiler can target spill instructions to use the CCM, moving most compiler-inserted memory traffic out of the pathway to main memory and eliminating any impact that those spill instructions would have on the state of the main memory hierarchy. Such memories already exist on some DSP microprocessors. Our techniques can be applied directly on those chips.This paper presents two compiler-based methods to exploit such a memory, along with experimental results showing that speedups from using CCM may be sizable. It shows that using the register allocation's coloring paradigm to assign spilled values to memory can greatly reduce the amount of memory required by a program.
Starting Page 2
Ending Page 11
Page Count 10
File Format PDF
ISBN 1581131070
DOI 10.1145/291069.291010
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 1998-10-01
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
  • About
  • Disclaimer
  • Feedback
  • Sponsor
  • Contact
  • Chat with Us
About National Digital Library of India (NDLI)
NDLI logo

National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.

Learn more about this project from here.

Disclaimer

NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.

Feedback

Sponsor

Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.

Contact National Digital Library of India
Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302
See location in the Map
03222 282435
Mail: support@ndl.gov.in
Sl. Authority Responsibilities Communication Details
1 Ministry of Education (GoI),
Department of Higher Education
Sanctioning Authority https://www.education.gov.in/ict-initiatives
2 Indian Institute of Technology Kharagpur Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project https://www.iitkgp.ac.in
3 National Digital Library of India Office, Indian Institute of Technology Kharagpur The administrative and infrastructural headquarters of the project Dr. B. Sutradhar  bsutra@ndl.gov.in
4 Project PI / Joint PI Principal Investigator and Joint Principal Investigators of the project Dr. B. Sutradhar  bsutra@ndl.gov.in
Prof. Saswat Chakrabarti  will be added soon
5 Website/Portal (Helpdesk) Queries regarding NDLI and its services support@ndl.gov.in
6 Contents and Copyright Issues Queries related to content curation and copyright issues content@ndl.gov.in
7 National Digital Library of India Club (NDLI Club) Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach clubsupport@ndl.gov.in
8 Digital Preservation Centre (DPC) Assistance with digitizing and archiving copyright-free printed books dpc@ndl.gov.in
9 IDR Setup or Support Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops idr@ndl.gov.in
I will try my best to help you...
Cite this Content
Loading...