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SMLNJ : Intel x 86 back end Compiler Controlled Memory
| Content Provider | Semantic Scholar |
|---|---|
| Author | George, Lal |
| Copyright Year | 2007 |
| Abstract | This note describes the code generation algorithm used for the Intel x86, introduced in version 110.16. The standard Chaitin graph coloring register allocation cannot be used directly for machines with few registers, as all temporaries wind up being spilled, making for a poor allocation[Cha82]. Thus, for the x86, the conceptual model of the architecture has been extended with a set of memory locations that are treated as registers. The net effect is one where temporaries are computed into memory locations and passed as arguments to functions. The use of these memory locations managed in this way can be as fast as using registers, where the register allocation algo rithm is indirectly taking the hardware register renaming mechanism into account. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.smlnj.org/compiler-notes/k32.ps |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
