NDLI: Drowsy region-based caches: minimizing both dynamic and static power dissipation

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Drowsy region-based caches: minimizing both dynamic and static power dissipation

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Drowsy region-based caches: minimizing both dynamic and static power dissipation

Content Provider	ACM Digital Library
Author	Tyson, Gary S. McKee, Sally A. Geiger, Michael J.
Abstract	Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal partitioning reduces average power per data access by employing multiple smaller structures or using cache subbanks. For instance, region-based caching places small caches dedicated to stack and global accesses next to the L1 data cache. With respect to static power dissipation, leakage power may be addressed at both circuit and architectural levels. Drowsy caches reduce leakage power by keeping inactive lines in a low-power mode. Here we merge drowsy and region-based caching to reduce overall cache power consumption, showing that the combination yields more benefits than either alone. Applications from the MiBench suite exhibit power reductions in the cache system of up to 68-71%, depending on memory configuration, with a small increase in execution time.
Starting Page	378
Ending Page	384
Page Count	7
File Format	PDF
ISBN	1595930191
DOI	10.1145/1062261.1062322
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-05-04
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Energy-aware design Region-based caches Drowsy caches
Content Type	Text
Resource Type	Article

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