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  1. Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '00)
  2. The RACE II engine for real-time volume rendering
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Algorithms for division free perspective correct rendering
Tiled polygon traversal using half-plane edge functions
Polygon rendering on a stream architecture
Hardware-accelerated free-form deformation
Towards hardware implementation of loop subdivision
Towards interactive bump mapping with anisotropic shift-variant BRDFs
Adaptive view dependent tessellation of displacement maps
Single-pass full-screen hardware accelerated antialiasing
Prefiltered antialiased lines using half-plane distance functions
Tracking graphics state for networked rendering
Hybrid sort-first and sort-last parallel rendering with a cluster of PCs
Interactive volume on standard PC graphics hardware using multi-textures and multi-stage rasterization
GI-cube: an architecture for volumetric global illumination and rendering
The RACE II engine for real-time volume rendering

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Real-Time Graphics Rendering Engine

Book

The RACE II engine for real-time volume rendering

Content Provider ACM Digital Library
Author Ray, Harvey Silver, Deborah
Abstract In this paper, we present the RACE II Engine, which uses a hybrid volume rendering methodology that combines algorithmic and hardware acceleration to maximize ray casting performance relative the total amount of volume memory throughput contained in the system. The challenge for future volume rendering accelerators will be the ability to process higher resolution datasets at over 10Hz without utilizing large-scale, and therefore, expensive designs. The limiting performance factor for large datasets will be the throughput between the volume memory subsystem and computational units. Unfortunately, the throughput between memory devices and computational units does not scale with Moore's law. As a result, memory efficient solutions are needed that maximize the input-output relationship between volume memory throughput and frame rate. The RACE II design utilizes this approach and achieves an input-output relationship of up to 4 × larger than many solutions proposed in literature. As a result, this architecture is well suited for meeting the challenges of next generation datasets.
Starting Page 129
Ending Page 136
Page Count 8
File Format PDF
ISBN 1581132573
DOI 10.1145/346876.348248
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2000-08-01
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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