NDLI: ZSim: fast and accurate microarchitectural simulation of thousand-core systems

Please wait, while we are loading the content...

Continuous real-world inputs can open up alternative accelerator designs

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Agile, efficient virtualization power management with low-latency server power states

Microarchitectural mechanisms to exploit value structure in SIMT architectures

Quantum rotations: a case study in static and dynamic machine-code generation for quantum computers

Exploring memory consistency for massively-threaded throughput-oriented processors

Efficient virtual memory for big memory servers

Cooperative boosting: needy versus greedy power management

Orchestrated scheduling and prefetching for GPGPUs

Reducing memory access latency with asymmetric DRAM bank organizations

Bit mapping for balanced PCM cell programming

ZSim: fast and accurate microarchitectural simulation of thousand-core systems

The locality-aware adaptive cache coherence protocol

On the feasibility of online malware detection with performance counters

Virtualizing power distribution in datacenters

Deconfigurable microprocessor architectures for silicon debug acceleration

Flicker: a dynamically adaptive architecture for power limited multicore systems

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

Secure I/O device sharing among virtual machines on multiple hosts

Triggered instructions: a control paradigm for spatially-programmed architectures

DNA-based molecular architecture with spatially localized components

WeeFence: toward making fences free in TSO

Navigating big data with high-throughput, energy-efficient data partitioning

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM

Tri-level-cell phase change memory: toward an efficient and reliable memory system

GPUWattch: enabling energy optimizations in GPGPUs

A new perspective for efficient virtual-cache coherence

Design space exploration and optimization of path oblivious RAM in secure processors

Bubble-flux: precise online QoS management for increased utilization in warehouse scale computers

QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs

Convolution engine: balancing efficiency & flexibility in specialized computing

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates

Improving virtualization in the presence of software managed translation lookaside buffers

Utility-based acceleration of multithreaded applications on asymmetric CMPs

AC-DIMM: associative computing with STT-MRAM

Robust architectural support for transactional memory in the power architecture

LINQits: big data on little clients

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation

Die-stacked DRAM caches for servers: hit ratio, latency, or bandwidth? have it all with footprint cache

Zombie memory: Extending memory lifetime by reviving dead blocks

Studying multicore processor scaling via reuse distance analysis

Protozoa: adaptive granularity cache coherence

SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip

Whare-map: heterogeneity in "homogeneous" warehouse-scale computers

Non-race concurrency bug detection through order-sensitive critical sections

Thin servers with smart pipes: designing SoC accelerators for memcached

Improving memory scheduling via processor-side load criticality information

STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction execution

Catnap: energy proportional multiple network-on-chip

SIMD divergence optimization through intra-warp compaction

Resilient die-stacked DRAM caches

QuickSAN: a storage area network for fast, distributed, solid state disks

Criticality stacks: identifying critical threads in parallel programs using synchronization behavior

ZSim: fast and accurate microarchitectural simulation of thousand-core systems

Content Provider	ACM Digital Library
Author	Kozyrakis, Christos Sanchez, Daniel
Abstract	Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequential simulation even slower. Existing parallel simulation techniques either scale poorly due to excessive synchronization, or sacrifice accuracy by allowing event reordering and using simplistic contention models. As a result, most researchers use sequential simulators and model small-scale systems with 16-32 cores. With 100-core chips already available, developing simulators that scale to thousands of cores is crucial. We present three novel techniques that, together, make thousand-core simulation practical. First, we speed up detailed core models (including OOO cores) with instruction-driven timing models that leverage dynamic binary translation. Second, we introduce bound-weave, a two-phase parallelization technique that scales parallel simulation on multicore hosts efficiently with minimal loss of accuracy. Third, we implement lightweight user-level virtualization to support complex workloads, including multiprogrammed, client-server, and managed-runtime applications, without the need for full-system simulation, sidestepping the lack of scalable OSs and ISAs that support thousands of cores. We use these techniques to build zsim, a fast, scalable, and accurate simulator. On a 16-core host, zsim models a 1024-core chip at speeds of up to 1,500 MIPS using simple cores and up to 300 MIPS using detailed OOO cores, 2-3 orders of magnitude faster than existing parallel simulators. Simulator performance scales well with both the number of modeled cores and the number of host cores. We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.
Starting Page	475
Ending Page	486
Page Count	12
File Format	PDF
ISBN	9781450320795
DOI	10.1145/2485922.2485963
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-06-23
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems (2013)

Zsim: fast and accurate microarchitectural simulation of thousand-core systems.

ZSim:fast and accurate microarchitectural simulation of thousand-core systems

GPGPU-Accelerated Instruction Accurate and Fast Simulation of Thousand-core Platforms

1 gpgpu-accelerated instruction accurate and fast simulation of thousand-core platforms.

Zsim: a fast architectural simulator for isa design-space exploration.

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms

An effective synchronization approach for fast and accurate multi-core instruction-set simulation

Accurate and efficient regression modeling for microarchitectural performance and power prediction

ZSim: fast and accurate microarchitectural simulation of thousand-core systems

Similar Documents

ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems (2013)

Zsim: fast and accurate microarchitectural simulation of thousand-core systems.

ZSim:fast and accurate microarchitectural simulation of thousand-core systems

GPGPU-Accelerated Instruction Accurate and Fast Simulation of Thousand-core Platforms

1 gpgpu-accelerated instruction accurate and fast simulation of thousand-core platforms.

Zsim: a fast architectural simulator for isa design-space exploration.

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms

An effective synchronization approach for fast and accurate multi-core instruction-set simulation

Accurate and efficient regression modeling for microarchitectural performance and power prediction

ZSim: fast and accurate microarchitectural simulation of thousand-core systems