NDLI: Triggered instructions: a control paradigm for spatially-programmed architectures

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Triggered instructions: a control paradigm for spatially-programmed architectures

Content Provider	ACM Digital Library
Author	Gambhir, Mohit Parashar, Angshuman Allmon, Randy Maresh, Stephen Emer, Joel Lustig, Daniel Pavlov, Vladimir Zhai, Antonia Adler, Michael Jaleel, Aamer Rayess, Rachid Pellauer, Michael Crago, Neal Ahsan, Bushra
Abstract	In this paper, we present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid over-serialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture. Our analysis shows that a triggered-instruction based spatial accelerator can achieve 8X greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64% respectively over a program-counter style spatial baseline, resulting in a speedup of 2.0X.
Starting Page	142
Ending Page	153
Page Count	12
File Format	PDF
ISBN	9781450320795
DOI	10.1145/2485922.2485935
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-06-23
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Reconfigurable accelerators Spatial programming
Content Type	Text
Resource Type	Article

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